3D Physical Design Engineer

<div class="content-intro"><p><span data-contrast="none">Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. </span><span data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335559685":0,"335559737":240,"335559738":240,"335559739":240,"335559740":279}"> </span></p> <p>Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. <a href="https://openai.com/index/cerebras-partnership/">OpenAI recently announced a multi-year partnership with Cerebras</a>, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. </p> <p>Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.</p></div><p><strong>About The Role</strong></p> <p><span data-contrast="auto">As a member of our tight knit physical design team, you will be working on the design and analysis of 3D integrated products. This role involves a combination of traditional ASIC/SoC physical design skills, packaging, power, clock and cooling analysis. You will work closely with the architecture and RTL team to do RD on novel concepts for 3D integration.</span><span data-ccp-props="{"201341983":0,"335559740":240}"> </span></p> <p><strong><span data-contrast="auto">Skills and Qualifications</span></strong></p> <p><strong><span data-contrast="none">Required</span><span data-ccp-props="{"201341983":0,"335559740":240}"> </span></strong></p> <ul> <li><span data-contrast="auto"> 10+ years of physical design/verification experience.</span><span data-ccp-props="{"201341983":0,"335559740":240}"> </span></li> <li><span data-contrast="auto"> Strong knowledge of block level and full-chip physical verification methodology.</span><span data-ccp-props="{"201341983":0,"335559740":240}"> </span></li> <li><span data-contrast="auto"> Expert at optimizing for the best power/performance and area.</span></li> <li><span data-contrast="auto"> Experience with the complete physical design flow. Knowledge of Synopsys tool suite is a plus.</span><span data-ccp-props="{"201341983":0,"335559740":240}"> </span></li> <li><span data-contrast="auto"> Expert with ICV or Calibre tools resolving block and full-chip DRC and LVS issues.</span><span data-ccp-props="{"201341983":0,"335559740":240}"> </span></li> <li><span data-contrast="auto"> Expert with IR/EM analysis and resolution.</span></li> <li><span data-contrast="auto"> Strong ability in scripting languages like Tcl and Python. Ability to make flow enhancements.</span><span data-ccp-props="{"201341983":0,"335559740":240}"> </span></li> <li><span data-contrast="auto"> Demonstrated ability to work with RTL teams to optimize for physical design.</span></li> <li><span data-contrast="none"> Knowledge of 2.5D or 3D packaging solutions.</span></li> </ul> <p><strong><span data-contrast="auto">Preferred</span></strong><span data-contrast="auto"><strong> </strong> </span><span data-ccp-props="{"201341983":0,"335559740":240}"> </span></p> <ul> <li><span data-contrast="auto"> Experience doing full chip floor planning and integration. </span><span data-ccp-props="{"201341983":0,"335559740":240}"> </span></li> <li><span data-contrast="auto"> Knowledge of clock distribution.</span></li> <li><span data-contrast="auto"> Knowledge of cool ... (truncated, view full listing at source)