AI Silicon Physical Design Engineer

<div class="content-intro"><p><span data-contrast="none">Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. </span><span data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335559685":0,"335559737":240,"335559738":240,"335559739":240,"335559740":279}"> </span></p> <p>Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. <a href="https://openai.com/index/cerebras-partnership/">OpenAI recently announced a multi-year partnership with Cerebras</a>, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. </p> <p>Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.</p></div><p><strong><span data-contrast="none"><span data-ccp-parastyle="heading 5">About The Role</span></span></strong><span data-ccp-props="{"134245418":true,"134245529":true,"335559738":333,"335559739":333}"> </span></p> <p><span data-contrast="auto">Join our close-knit physical design team where you'll excel in synthesizing, placing, and routing high speed designs. Experience the full spectrum of physical design and implementation, collaborating closely with the RTL team and integrating these blocks seamlessly into the full-chip architecture.</span><span data-ccp-props="{"335559738":240,"335559739":240}"> </span></p> <p><strong><span data-contrast="none"><span data-ccp-parastyle="heading 5">Skills Qualifications</span></span></strong><span data-ccp-props="{"134245418":true,"134245529":true,"335559738":333,"335559739":333}"> </span></p> <ul> <li><span data-contrast="auto">10+ years of physical design physical verification experience.</span><span data-ccp-props="{"335559685":720,"335559739":0}"> </span></li> <li><span data-contrast="auto">Strong knowledge of block level and full-chip physical verification methodology.</span><span data-ccp-props="{"335559685":720,"335559739":0}"> </span></li> <li><span data-ccp-props="{"335559685":720,"335559739":0}"><span data-olk-copy-source="MessageBody">Strong experience in block/subsystem timing closure.</span></span></li> <li><span data-contrast="auto">Expert at optimizing for the best power/performance and area.</span></li> <li><span data-contrast="auto">Experience with the complete physical design flow. Knowledge of Synopsys tool suite is a plus.</span><span data-ccp-props="{"335559685":720,"335559739":0}"> </span></li> <li><span data-contrast="auto">Expert with ICV or Calibre tools resolving block and full-chip DRC and LVS issues.</span><span data-ccp-props="{"335559685":720,"335559739":0}"> </span></li> <li><span data-contrast="auto">Expert with IR/EM analysis and resolution.</span></li> <li><span data-contrast="auto">Good understanding of full chip floor planning and integration. </span><span data-ccp-props="{"335559685":720,"335559739":0}"> </span></li> <li><span data-contrast="auto">Strong ability in scripting languages like Tcl and Python. Ability to make flow enhancements.</span><span data-ccp-props="{"335559685":720,"335559739":0}"> </span></li> <li><span data-contrast="auto">Demonstrated ability to work with RTL teams to optimize for physical design.</span><span data-ccp-props="{"335559685":720,"335559739":0}"> </span></li> <li><span data-contrast="auto">Knowledge ... (truncated, view full listing at source)