Electrical Engineer

<div class="content-intro"><p><span data-contrast="none">Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. </span><span data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335559685":0,"335559737":240,"335559738":240,"335559739":240,"335559740":279}"> </span></p> <p>Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. <a href="https://openai.com/index/cerebras-partnership/">OpenAI recently announced a multi-year partnership with Cerebras</a>, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. </p> <p>Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.</p></div><p><strong><span data-contrast="none">Responsibilities</span></strong><span data-ccp-props="{"134233117":false,"134233118":false,"335551550":0,"335551620":0,"335559738":0,"335559739":0}"> </span></p> <ul> <li data-leveltext="%1." data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":1,"335552541":0,"335559683":0,"335559684":-1,"335559685":720,"335559991":360,"469769242":[65533,0,46],"469777803":"left","469777804":"%1.","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="none">Lead printed circuit board design through all development stages: from definition to implementation, bring-up, qualification, and production release.</span><span data-ccp-props="{"134233117":false,"134233118":false,"335551550":0,"335551620":0,"335559738":0,"335559739":0}"> </span></li> </ul> <ul> <li data-leveltext="%1." data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":1,"335552541":0,"335559683":0,"335559684":-1,"335559685":720,"335559991":360,"469769242":[65533,0,46],"469777803":"left","469777804":"%1.","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1"><span data-contrast="none">Full responsibility for electrical specification, schematic design, components selection, and layout considerations.</span><span data-ccp-props="{"134233117":false,"134233118":false,"335551550":0,"335551620":0,"335559738":0,"335559739":0}"> </span></li> </ul> <ul> <li data-leveltext="%1." data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":1,"335552541":0,"335559683":0,"335559684":-1,"335559685":720,"335559991":360,"469769242":[65533,0,46],"469777803":"left","469777804":"%1.","469777815":"hybridMultilevel"}" data-aria-posinset="3" data-aria-level="1"><span data-contrast="none">Extensive lab bring-up and debugging, including developing automated benchtop setups for board characterization.</span><span data-ccp-props="{"134233117":false,"134233118":false,"335551550":0,"335551620":0,"335559738":0,"335559739":0}"> </span></li> </ul> <ul> <li data-leveltext="%1." data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":1,"335552541":0,"335559683":0,"335559684":-1,"335559685":720,"335559991":360,"469769242":[65533,0,46],"469777803":"left","469777804":"%1.","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="1"><span data-contrast="none">Collaborate with various design and operations teams: manufacturing operations test engineering, supply chain, ASIC, mechanical, signal integrity, power delivery, layout, embedded ... (truncated, view full listing at source)