Lead RTL Design Engineer

<div class="content-intro"><p><span data-contrast="none">Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. </span><span data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335559685":0,"335559737":240,"335559738":240,"335559739":240,"335559740":279}"> </span></p> <p>Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. <a href="https://openai.com/index/cerebras-partnership/">OpenAI recently announced a multi-year partnership with Cerebras</a>, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. </p> <p>Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.</p></div><h4 class="x_elementToProof">About The Role</h4> <div class="x_elementToProof">As a lead front-end design engineer, you will be a key part of the world-class team designing and developing the next generations of the Cerebras Wafer Scale Engine (WSE). This role requires deep expertise in RTL design and integration, with a strong focus on delivering high-performance, power-efficient, and scalable solutions. <span class="Apple-converted-space"> </span>The role also requires close collaboration and management of external ASIC vendor. You will collaborate closely with the design verification, physical design, software and system teams to bring innovative semiconductor architectures from concept to production, addressing the unique challenges of building WSE systems.</div> <div class="x_elementToProof"> </div> <div class="x_elementToProof"><strong>Responsibilities</strong></div> <ul> <li> <div>Drive all aspects of chip design, including Functional Specification, Micro-architecture, RTL development, Synthesis.</div> </li> <li> <div class="x_elementToProof">Managing external ASIC vendor through product development cycle.</div> </li> <li> <div class="x_elementToProof">Work closely with PD team members for design closure to meet PPA goals.</div> </li> <li> <div class="x_elementToProof">Work closely with Design verification and DFT teams for achieving the best functional and test coverage.</div> </li> <li> <div>Work with software and system teams to understand opportunities to deliver optimal performance and feature set for the product.</div> </li> <li> <div>Debug silicon-level functional, timing, and power issues during bring up.</div> </li> </ul> <div class="x_elementToProof"><strong>Requirements</strong></div> <ul> <li>Master’s degree in Computer Science, Electrical Engineering, or equivalent.</li> <li>Can work in a hybrid work environment. </li> <li> <div>8-15 years of experience in delivering complex, high performance high quality RTL designs.</div> </li> <li> <div>Experience with Front End Chip integration and third-party IP integration.</div> </li> <li> <div>Demonstrated experience in networking, high-performance computing, machine learning or related fields.</div> </li> <li> <div>Proven track record of multiple silicon success.</div> </li> <li> <div>Experience collaborating and managing external vendors.</div> </li> <li> <div>Experience with designing/integrating high speed IO.</div> </li> <li> <div>Networking stack experience including TCP/IP, RDMA and Ethernet.</div> </li> <li> <div>Knowledge of PCIe, CPU in ... (truncated, view full listing at source)