Senior IC Design Engineer – IO Signal Integrity & Power Delivery

<div class="content-intro"><p><span data-contrast="none">Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. </span><span data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335559685":0,"335559737":240,"335559738":240,"335559739":240,"335559740":279}"> </span></p> <p>Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. <a href="https://openai.com/index/cerebras-partnership/">OpenAI recently announced a multi-year partnership with Cerebras</a>, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. </p> <p>Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.</p></div><p><span data-contrast="auto">Senior IC Design Engineer – IO Signal Integrity Power Delivery</span><span data-ccp-props="{}"> </span></p> <p><strong><span data-contrast="auto">About the Role</span></strong><span data-ccp-props="{}"> </span></p> <p><span data-contrast="auto">In this role, you’ll be at the center of high-speed IO interface design and integration, driving the signal integrity (SI) and power delivery (PI) performance of custom IP within our wafer-scale engine.</span><span data-ccp-props="{}"> </span></p> <p><span data-contrast="auto">This position emphasizes complete system analysis, architecture, integration and circuit design from transistor level to external voltage regulator, to ensure that custom and third-party IP meets performance, power, and reliability targets across die, 3d assembly, and system level boundaries.</span><span data-ccp-props="{}"> </span></p> <p><span data-contrast="auto">You’ll collaborate closely with design, packaging, and system engineers to architect and validate custom DDR-like interfaces, IO circuits, and power delivery networks. This is a hands-on technical leadership role for an engineer who understands how circuit behavior, interconnect design, and system integration combine to define product success.</span><span data-ccp-props="{}"> </span></p> <p><strong><span data-contrast="auto">Key Responsibilities</span></strong><span data-ccp-props="{}"> </span></p> <ul> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="auto">Own IO signal integrity and power delivery analysis for custom and third-party IP integration in full system stack: die level, 3d integration, board level</span><span data-ccp-props="{}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1"><span data-contrast="auto">Define interface architecture and design specifications, including signaling schemes, impedance targets, and power distribution requirements.</span><span data-ccp-props="{}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"3355 ... (truncated, view full listing at source)