Senior Technical Program Manager – AI Infrastructure, Site Operations

<div class="content-intro"><p><span data-contrast="none">Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. </span><span data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335559685":0,"335559737":240,"335559738":240,"335559739":240,"335559740":279}"> </span></p> <p>Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. <a href="https://openai.com/index/cerebras-partnership/">OpenAI recently announced a multi-year partnership with Cerebras</a>, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. </p> <p>Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.</p></div><h4>About The Role</h4> <p class="x_p1"><span data-olk-copy-source="MessageBody">This Sr. TPM role owns site and data center operations programs supporting Cerebras’ AI Cloud and customer deployments. The position sits at Sunnyvale HQ and works closely with Hardware Engineering, Inference Engineering, and Operations leadership to ensure Cerebras systems are reliably deployed, operated, and scaled.</span></p> <p class="x_p1">This is a highly technical, execution-focused TPM role with strong emphasis on operational readiness, cross-functional coordination, and metrics/KPIs.</p> <h4 class="x_p1">Responsibilities </h4> <ul> <li class="x_p1" data-olk-copy-source="MessageBody">Own end-to-end technical programs for data center and site operations</li> <li class="x_p1">Act as single-threaded owner across: <ul> <li class="x_p1">Hardware Systems Engineering</li> <li class="x_p1">AI Cloud Infrastructure Operations</li> <li class="x_p1">Network Storage Engineering</li> <li class="x_p1">Facilities, power, cooling, and colo partners</li> </ul> </li> <li class="x_p1">Drive site readiness for Cerebras Wafer-Scale Engine systems</li> <li class="x_p1">Partner on installation, commissioning, change management, and break/fix workflows</li> <li class="x_p1">Lead incident reviews and postmortems; ensure corrective actions are closed</li> <li class="x_p1">Define and own operational metrics and KPIs, including: <ul> <li class="x_p1">Availability and reliability</li> <li class="x_p1">Incident rate, severity, MTTR / MTTD</li> <li class="x_p1">Deployment readiness and time-to-service</li> <li class="x_p1">Capacity and operational risk</li> </ul> </li> <li class="x_p1">Build executive-level dashboards and reporting</li> <li class="x_p1">Establish program governance, risk tracking, and RACI clarity</li> <li class="x_p1">Present program status, metrics, and operational risks to senior leadership</li> </ul> <h4 class="x_p1"><strong>Required Background </strong></h4> <ul> <li class="x_p1" data-olk-copy-source="MessageBody">8+ years in Technical Program Management, Infrastructure Ops, or Data Center Ops</li> <li class="x_p1">Experience leading large, cross-functional infrastructure programs</li> <li class="x_p1">Strong understanding of: <ul> <li class="x_p1">Data center power and cooling fundamentals</li> <li class="x_p1">Network and storage basics</li> <li class="x_p1">Hardware-centric platforms</li> </ul> </li> <li class="x_p1">Proven ability to define and operationalize metrics</li> <li class="x_p1">Strong written and executive-level co ... (truncated, view full listing at source)