Senior Yield Enhancement Engineer

<div class="content-intro"><p><span data-contrast="none">Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. </span><span data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335559685":0,"335559737":240,"335559738":240,"335559739":240,"335559740":279}"> </span></p> <p>Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. <a href="https://openai.com/index/cerebras-partnership/">OpenAI recently announced a multi-year partnership with Cerebras</a>, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. </p> <p>Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.</p></div><p><strong><span data-contrast="none">The Role</span></strong><span data-contrast="none">: Senior Yield Enhancement Engineer</span><span data-ccp-props="{"335557856":16777215}"> </span></p> <p><span data-contrast="none">We are seeking a highly experienced Senior VLSI Product and Test Engineer with </span><strong><span data-contrast="none">7+ years </span></strong><span data-contrast="none">of relevant experience in Semiconductor Testing/Failure Analysis/Yield Enhancement. The successful candidate will look at ATE datalogs, understand the defects in detail, disposition wafers based on ATE data and drive FA/Yield enhancement using physical/optical inspection techniques used in FA.</span><span data-ccp-props="{"335559738":240,"335559739":240}"> </span></p> <p><span data-contrast="none">Suitable candidate will have depth in testing, characterization of silicon defects, failure modes, and experience delivering end-to-end solutions working closely with teams across chip design, fabrication, validation, production, and manufacturing.</span><span data-ccp-props="{"335559738":240,"335559739":240}"> </span></p> <p><strong><span data-contrast="none">Key Responsibilities </span></strong><span data-ccp-props="{"335557856":16777215}"> </span></p> <ul> <li data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="auto">Analyze ATE data logs, Shmoo plots, parametric characterization data, and spatial wafer defect patterns.</span><span data-ccp-props="{"335559739":0}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1"><span data-contrast="auto">Develop failure analysis tools using optical, photo emission, and laser-based defect localization techniques specific to Cerebras hardware.</span><span data-ccp-props="{"335559739":0}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="3" data-aria-level="1"><span data-contrast=" ... (truncated, view full listing at source)