Lab HW Engineer
CiscoSan Jose, California, US$153k – $219kPosted 8 May 2026
Tech Stack
Job Description
The application window is expected to close on: 05/08/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. Meet the team: The Hardware Team is responsible for leading the hardware development through all phases of product design, from concept and architecture to production and support. Our engineers handle every aspect of chip development, from definition and architecture to silicon bring-up, validation, and system integration. This role combines strong technical expertise with leadership, planning, and cross-functional collaboration. Your Impact: You will join our Cisco Silicon One team, the epicenter of Cisco’s ASIC design. As a Hardware Lab Engineer you will be responsible for enabling and supporting the full lifecycle of silicon and hardware development by operating and evolving a world-class hardware lab environment. Key responsibilities: Own and manage day-to-day operation of the hardware lab supporting ASIC bring-up, EVB development, validation, and system debug. Ensure lab readiness for critical milestones such as silicon power-on, bring-up, qualification, and customer enablement. Provide hands-on technical support in the lab for EVB bring-up, debug, failure analysis Manage lab infrastructure, equipment, and resources including scopes, analyzers, power supplies, sockets, pogo pins, handlers, and automation tools. Coordinate lab usage and priorities across multiple projects and global teams. Work closely with cross-functional teams including board design, package, mechanical, thermal, SI/PI, test, production, and validation. Drive continuous improvement of lab processes, workflows, safety, and efficiency. Interface with external vendors and partners for lab equipment, sockets, and manufacturing support. Support remote teams and cross-site collaboration by hosting and managing shared lab resources. Minimum Qualifications: Bachelors in Electrical Engineering or related field with 5+ years of experience in hardware labs, silicon validation, EVB bring-up, or system-level debug. Prior hands-on experience with lab equipment (oscilloscopes, logic analyzers, power supplies, thermal tools). Prior experience supporting ASIC or SoC bring-up and validation. Prior experience with sockets, pogo pins, packages, and mechanical constraints. Preferred Qualifications: Hardware-oriented, with strong lab presence and troubleshooting skills Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada: The starting salary range posted for this position is $152,500.00 to $219,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits. Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees are off ... (truncated, view full listing at source)
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