Senior PCB Design Engineer

<p><strong>Who You’ll Work With</strong></p><p>Working closely with cross-functional teams including Hardware Design, Signal Integrity (SI), Power Integrity (PI), Mechanical Engineering, Thermal Engineering, and Manufacturing, our engineers innovate on system architectures and ultra-high-speed PCB designs to deliver state-of- the-art networking platforms.</p><p><strong>What You'll Do</strong></p><p>Our Hardware Design Engineering team is at the forefront of developing high-speed networking and Ethernet products used in enterprise campuses, hyperscale datacenters, and next-generation AI clusters. The team is responsible for end-to-end design and development of advanced hardware solutions that meet the demands of modern networking environments — including optical interface platforms up to 800G and 1.6T.</p><p><strong>Core Responsibilities</strong></p><p>&#xa0;High-Speed Layout &amp; Routing</p><ul><li>Implement complex routing for advanced interfaces such as 112G/224G SerDes, PCIe Gen 5/6, DDR4/5/6</li><li>Design and route high-speed differential pairs with tight skew and impedance control</li><li>Execute dense BGA fan-out for high-pin-count ASICs and FPGAs</li></ul><p>Optical Transceiver PCB Layout (800G / 1.6T)</p><ul><li>Design and layout boards supporting high-bandwidth optical transceivers (QSFP-DD, OSFP, OSFP-XD or equivalent)</li><li>Route 112G / 224G PAM4 electrical channels between switch ASICs and optical modules</li><li>Define insertion loss budgets and coordinate with SI engineers to meet IEEE compliance requirements</li><li>Optimize breakout routing beneath high-density optical cages</li><li>Implement via stub mitigation strategies including backdrilling for ultra-high-speed signal paths</li><li>Manage ground reference continuity, EMI control, and return path integrity near optical connectors</li><li>Consider thermal dissipation (20W–30W+ modules) in layout planning</li></ul><p>Impedance Control &amp;amp; Signal Integrity</p><ul><li>Design advanced multi-layer stack-ups (20–30+ layers)</li><li>Calculate impedance profiles and ensure low-reflection, low-crosstalk performance</li><li>Collaborate with SI teams on channel modeling and pre-/post-layout simulations</li></ul><p>Power Integrity (PI) Optimization</p><ul><li>Design robust Power Distribution Networks (PDNs) for high-current ASICs</li><li>Layout multi-phase DC/DC converters for high transient loads</li><li>Strategically place decoupling capacitors to ensure wideband impedance stability</li></ul><p>Thermal &amp;amp; Mechanical Coordination</p><ul><li>Integrate thermal vias, heat sink attachments, and high-conductivity materials</li><li>Coordinate mechanical constraints such as enclosure, airflow, and structural limitations</li><li>Ensure proper placement and structural integration of optical cages</li></ul><p>Advanced Fabrication Deliverables</p><ul><li>Generate comprehensive manufacturing packages (Gerber, ODB++, IPC-2581)</li><li>Define backdrilling parameters and impedance specifications</li><li>Ensure compliance with DFM, DFA, and DFT requirements</li><li>Support boards through fabrication, assembly, and production ramp</li></ul><p>Library &amp;amp; Feasibility Ownership</p><ul><li>Create and maintain high-density component footprints (e.g., large BGAs, optical module connectors)</li><li>Participate in new product feasibility studies</li><li>Develop detailed routing guidelines and work packages for layout partners</li><li>Review external placement and routing work to ensure quality and schedule adherence</li></ul> <ul><li>Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or related field</li><li>10+ years of relevant hardware engineering experience</li><li>Proven experience designing networking hardware, particularly involving 100G/200G PAM4 Ethernet switching</li><li>Direct experience in high-speed optical transceiver PCB layout (800G and/or 1.6T preferred)</li><li>Expertise with 112G / 224G PAM4 routing and channel optimization</li><li ... (truncated, view full listing at source)