Director of Engineering

<div class="content-intro"><p><span data-contrast="none">Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. </span><span data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335559685":0,"335559737":240,"335559738":240,"335559739":240,"335559740":279}"> </span></p> <p>Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. <a href="https://openai.com/index/cerebras-partnership/">OpenAI recently announced a multi-year partnership with Cerebras</a>, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. </p> <p>Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.</p></div><p class="s7"><span class="s2">Cerebras Systems Inc. has multiple openings for Director of Engineering.</span></p> <p class="s7"><span class="s2">Title: Director of Engineering</span></p> <p><strong>Job Duties</strong></p> <ul> <li>Own the end-to-end verification roadmap for a next-gen wafer scale engine, establishing the formal, block/SOC UVM and gate-level simulation methodologies and ensuring successful project delivery.</li> <li>Sign off on the design verification of next-generation AI/ML accelerators by analyzing functional and code coverage, gate-level simulation results, regression trends, and reported bugs, leveraging AI/ML hardware verification expertise.</li> <li>Oversee verification and validation of complex architecture and design by defining test plans, testing methodologies and strategies in coordination with architecture, RTL, firmware, compiler, kernel and emulation teams.</li> <li>Direct, review, and approve design modifications and technical changes in engineering projects.</li> <li>Direct engineering staff in the preparation and evaluation of verification test cases using Verilog System Verilog hardware description languages, ensuring that testing processes meet project standards and technical requirements.</li> <li>Confer with executive management to discuss project specifications and timelines for next gen products.</li> <li>Provide updates on goals for monthly program reviews by using tools like Microsoft Power point, Excel and Word documentation.</li> <li>Develop standards and procedures for design verification work. Define roadmap, methodology and tools for performing design verification.</li> <li>Advocate and direct implementation of scripts and tools to automate process using scripting languages like python or perl.</li> <li>Establish technical goals within broad outlines provided by top management.</li> <li>Monitor progress against goals and report to executive management on progress against those goals using project tracking tools such as Confluence, Excel and Microsoft Project.</li> <li>Perform administrative functions, such as reviewing or writing reports, managing and approving contracts and expenditures, enforcing rules, or purchasing of materials or services.</li> <li>Give feedback to employees on their performance. Advise executive management on salary increase and stock awards.</li> <li>Direct recruitment, placement, and evaluation of engineering project staff.</li> </ul> <p><strong>Minimum Requirements:</strong></p> <p><span style="text-decoration: underline;"><strong>Mas ... (truncated, view full listing at source)