Senior ASIC Engineer - SDC

The application window is expected to close on: 03/06/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. The job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. This is an onsite role based in the San Jose, CA office. While the team may have hybrid days, this is at the discretion of the team and is subject to change at any time. Meet the Team: Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks. Cisco’s silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon organization and a large campus (with onsite gym, healthcare, and café, social interest groups, and philanthropy), with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. You will work with exceptional talent with vast ASIC design and development expertise. With Cisco being a systems company, you will also have an opportunity to work with other ASIC teams in the journey of taking it from concept to first customer shipments. Your Impact: You are a diligent Design/SDC Engineer with analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/STA tools and scripting for automation, you excel at identifying and resolving timing issues across all design levels. You will collaborate with Front-end and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure. As part of this team, you’ll contribute to developing next-generation networking chips. Responsibilities include: Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes. Option to also do block level RTL design or block or top-level IP integration. Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level. Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle. Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development. Creating fullchip clocking diagrams and related documentation. Minimum Qualifications: Bachelor’s Degree in Electrical or Computer Engineering with 2.5 + years of ASIC experience, OR Master’s Degree in Electrical or Computer Engineering with 1+ years of ASIC experience, OR PhD with + 1 year of ASIC experience. Experience with block/full chip SDC development in functional and test modes. Understanding of related digital design concepts (eg. clocking and async boundaries). Experience with synthesis tools (eg. Synopsys DC/DCG/FC), Verilog/System Verilog programming. Preferred Qualifications: Experience in Static Timing Analysis. Experience with constraint analyzer tools such as Fishtail/TCM (Timing Constraint Manager from Synopsys) and CCD (Conformal Constraint Designer from Cadence). Experience with Spyglass CDC and glitch analysis. Experience with STA tools such as PrimeTime/Tempus. Experience with scripting languages such as Python, Perl, or TCL. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the o ... (truncated, view full listing at source)