Signal and Power Integrity Technical Leader (Hybrid)

The application window is expected to close on: 04/24/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. This position requires that you live within commuting distance of our San Jose, CA office and commute to the office at least 3-4 days per week. Meet the Team Cisco Silicon One (#CiscoSiliconOne) is a business organization with a long track record of building complex and high-performance Silicon ASICs. Our silicon devices drive the world’s most complex networks and carry over 90% of IP traffic. Cisco Silicon One is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. We are a highly specialized ASIC team with experts in all aspects of advanced IC package design and heterogeneous system integration. Our substrates use the latest 2.5D fanout technologies for large-scale integration, using the latest signaling and data transfer technologies. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry! Your Impact We are seeking a highly qualified Signal and Power Integrity Technical Leader to help us develop our next generation ASIC packaging and lead our Silicon Packaging Signal and Power Integrity Team to define, design and verify ASIC packaging to be deployed in a range of Cisco platforms. Develop, document, and implement design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products. Analyze substrate signal integrity (SI) and power integrity (PI), providing feedback and collaborating with the layout team to develop optimal solutions across interposer, substrate, and PCB. Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting. Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and to resolve complex technical issues using advanced technology design rules. Define the processes, methods, and tools for the design and implementation of complex ASIC/package developments. Lead or participate in chip architecture discussions and the definition, architecture, and design of high-performance ASICs, including reviews of intricate IC and analog/mixed-signal circuit designs. Mentor and support the signal integrity team, junior engineers, and influence packaging/hardware teams, ensuring all technical specifications and innovative solutions are met. Develop and promote a culture of design reviews, postmortems, and continuous improvement across multi-disciplined engineering teams. Minimum Qualifications Bachelor's degree in Electrical Engineering and 10+ years of relevant signal and/or power integrity experience, or Master's degree in Electrical Engineering and 8+ years of relevant signal and/or power integrity experience, or PhD in Electrical Engineering and 5+ years of relevant signal and/or power integrity experience. Proven experience with multiple high-speed ASIC tape-outs. Deep expertise in 56G PAM4 and above, high-speed SerDes architectures, channel modeling, BER prediction, transmission line theory, and electromagnetics with a solid understanding of scattering and impedance network parameters. Extensive hands-on experience with Keysight ADS, Ansys HFSS/EM flow, and Cadence APD for layout review. Working knowledge of SPICE. Preferred Qualifications Prior experience leading small to medium technical teams. Skilled in articulating ideas and technical concepts to diverse audiences, both verbally and in writing. Experience with advanced nodes (5nm, 3nm and below). Background in high-bandwidth memory (HBM) or high-speed memory interf ... (truncated, view full listing at source)