Sr. Director, Hardware Engineering

The application window is expected to close on: 03/08/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms underpinning Cisco’s core Switching, Routing, and Wireless products. With approximately 2,100 employees in 16 countries, CHG provides networking hardware solutions for enterprises, service providers, the public sector, and non-profit organizations globally. Cisco Silicon One represents the industry’s only unifying silicon architecture, supporting unified routing and switching portfolios from Top-of-Rack switches to web-scale data centers. Join us to help shape Cisco’s revolutionary hardware solutions. Your Impact As Senior Director, Hardware Engineering, you will: Provide strategic leadership to a global team of Physical Design, Circuit Design, DFT, and Integration engineers, driving SoC Physical Design implementation in advanced process nodes. Collaborate with cross-functional teams—including Architecture, Package, PD, RTL, NPI, Packaging, DFT, and other engineering groups—to develop, optimize, and execute floorplans that meet Power, Performance, and Area (PPA) goals. Build and scale a high-performance team of technical leaders, fostering innovation and operational excellence. Develop execution schedules and track project milestones for complex ASIC development programs, ensuring alignment with business objectives. Review and refine ASIC design methodologies and flows, leading projects from concept to release. Drive technical reviews, risk assessments, and communication of status to senior management, with a focus on quality, schedule, and technical depth. Oversee the development and deployment of new automation utilities to enhance design quality and accelerate delivery timelines. Conduct EMIR analysis, timing signoff closure, and periodic deep-dive design reviews to maintain high standards. Maintain expert knowledge of both front-end (FE) and back-end (BE) ASIC flows, and drive PPA optimization. Minimum Qualifications 15+ years of experience in the hardware industry, including 7+ years in proven management of SoC and Physical Design teams, leading managers. Demonstrated success in leading and managing large-scale ASIC developments in advanced process nodes. Extensive hands-on experience in ASIC design and physical design execution scheduling. Strong track record of driving ASIC design methodologies from concept through release. Preferred Qualifications Expertise with industry-standard Place & Route (PnR) and signoff tools. Deep knowledge of block-level synthesis, place and route, timing closure, and advanced power analysis. Experience with scripting languages (Tcl, Python). Strong understanding of static timing analysis, design constraints, and power integrity. Ability to balance strategic vision with attention to execution detail. Self-motivated leader with a collaborative approach and the ability to manage highly cross-functional teams. MS or BS in Electrical Engineering or Computer Science. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying ... (truncated, view full listing at source)