High Performance Compute Responsible Engineer

Relativity Space
Long Beach, CaliforniaPosted 10 March 2026

Tech Stack

Job Description

At Relativity Space, we’re building rockets to serve today’s needs and tomorrow’s breakthroughs. Our Terran R vehicle will deliver customer payloads to orbit, meeting the growing demand for launch capacity. But that’s just the start. Achieving commercial success with Terran R will unlock new opportunities to advance science, exploration, and innovation, pioneering progress that reaches beyond the known. Joining Relativity means becoming part of something where autonomy, ownership, and impact exist at every level. Here, you're not just executing tasks; you're solving problems that haven’t been solved before, helping develop a rocket, a factory, and a business from the ground up. Whether you’re in propulsion, manufacturing, software, avionics, or a corporate function, you’ll collaborate across teams, shape decisions, and see your work come to life in record time. Relativity is a place where creativity and technical rigor go hand in hand, and your voice will help define the stories we’re writing together. Now is a unique moment in time where it’s early enough to leave your mark on the product, the process, and the culture, but far enough along that Terran R is tangible and picking up momentum. The most meaningful work of your career is waiting. Join us. About the Team: The Interplanetary Program was established to expand access to scientific exploration across our solar system. Its mission is to make planetary research faster, more affordable, and more capable than ever before by rethinking how science missions are designed, built, and operated . The program aims to enable scientists to send instruments to distant worlds without decades of development or prohibitive costs. By creating a sustainable model for interplanetary exploration, we are transforming space science from an occasional event into a continuous process of discovery that accelerates knowledge, broadens participation, and inspires the next generation of explorers . About the Role: You'll own the compute hardware from architecture through bring up — there's no hand-off to another team mid-stream. You pick the components, you design the board, you're the one powering it on and debugging it with the software team Design the compute boards that deliver ≥10 TFLOPS of processing power for onboard AI/ML inference and science data processing within the Relay Data Center, owning the hardware from schematic capture through board-level validation Architect and implement power delivery networks for high-complexity carrier boards, including 500W+ multi-rail designs with tight sequencing integrating GPU or CPU compute modules onto custom PCBs with high-speed coherent interconnects Define thermal interface requirements (power dissipation budgets, junction temperature limits, interface material selection) and hand off specifications to the mechanical team, who own the thermal and packaging solution Design and validate high-speed memory interfaces (HBM, DDR5), PCIe Gen 4/5 chip-to-chip links, and 10 GbE+ Ethernet connections to the payload network, along with board-level power monitoring, current limiting, and radiation upset recovery circuitry Lead hardware bringup and board-level validation. Diagnose and resolve issues hands-on while collaborating closely with the software engineers who are building the software environment on top of your hardware About You: BSEE with 5+ years designing and bringing up high-speed digital compute boards, ideally with direct exposure to GPU, HPC, or modern accelerator platforms Proficient in high-speed digital PCB design principles: multi-GHz signaling, dense BGA escape routing on high layer count stackups, and signal integrity analysis through both simulation and measurement Strong command of power integrity and power delivery network design, including multi-rail architectures, power management IC selection, voltage sequencing, and board-level current limiting Strong working experience with high-speed serial interface ... (truncated, view full listing at source)