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🍪 Privacy Notice This website uses cookies to improve your web experience. By using the site, you agree to the use of cookies. dismiss Senior Analog IC Layout Design Engineer Saratoga, CAE-Space US – Engineering, Manufacturing & Operations /On-Site APPLY FOR THIS JOB Ready to make connectivity from space universally accessible, secure and actionable? Then you’ve come to the right place! E-Space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems. We’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space-based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life. We are looking for a highly skilled Senior Analog IC Layout Design Engineer to join our dynamic team. The ideal candidate will have extensive experience in designing and optimizing the layout of analog and mixed-signal integrated circuits (ICs). You will work closely with circuit design engineers to translate schematics into high-performance, manufacturable layouts, ensuring adherence to design rules and specifications. What you will do: Perform full custom analog and mixed-signal IC layout design, including floor planning, placement, and routing of circuits such as amplifiers, data converters, voltage regulators, and RF components Collaborate closely with circuit design engineers to understand design specifications and ensure high-performance layout implementations Optimize layouts for performance metrics such as area, power, noise, parasitics, and matching Perform DRC (Design Rule Check), LVS (Layout Versus Schematic), and parasitic extraction using industry-standard tools (e.g., Cadence Virtuoso, Mentor Graphics Calibre) Conduct peer reviews of layout work, provide feedback, and mentor junior layout engineers Work with process and foundry engineers to understand and integrate process limitations and requirements into the layout design Ensure designs meet manufacturability standards and participate in post-layout simulation and validation Develop and maintain layout methodologies and documentation for efficient and consistent design practices What you bring to this role: 7+ years of experience in custom analog IC layout design Strong proficiency in using CAD tools for layout design (e.g., Cadence Virtuoso, Mentor Graphics Calibre, Synopsys IC Compiler, etc.) Extensive experience with analog layout techniques for minimizing noise, matching, and parasitic effects Deep understanding of semiconductor process technologies and design rules Proven track record of successful tape-outs of complex analog/mixed-signal ICs Excellent attention to detail and a methodical approach to design and validation Strong communication skills and ability to work effectively in cross-functional teams Bonus points for the following: Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, or a related field Experience with RF IC layout design Familiarity with scripting (e.g., Skill, Python) to automate layout tasks and improve productivity Knowledge of advanced nodes (e.g., 28nm, 14nm) and associated layout challenges This is a full time, exempt position, based out of our Saratoga office.  The target base pay for this position is $150,000 - $200,000 annually.  The total compensation packaged will be determined by various factors such as your relevant job-related knowledge, skills, and experience. We are redefining how satellites are designed, manufactured and used—so we’re looking for candidates with passion, deep knowledge and direct experience on LEO satellite component development, design and in-orbit activities. If that’s your experience – then we’ ... (truncated, view full listing at source)