Sr. CPU Logic Design Front end Methodology Engineer
Intel3 Locations$164k – $312kPosted 27 March 2026
Job Description
Job Details:
Job Description:
We developed the Intel microprocessors, a foundational technology that powers a diverse range of devices-from entry-level PCs to high-end gaming desktops and laptops, as well as data center solutions and many other applications. As part of our team, you will help design the next generation of high-performance microprocessors. We are looking for a skilled individual who has hands-on experience in RTL methodologies, coding, debug and effective use of AI tools and can provide technical leadership to deliver world-class products.
As a CPU RTL Methodology Engineer your responsibilities will include but are not limited to:
• Demonstrated leadership and hands-on experience in leveraging AI tools and methodologies to drive significant efficiency gains and improvements in RTL coding and other areas of silicon development.
• Proactively advances front-end methodologies and contributes to architectural and microarchitectural discussions to enhance scalability and flexibility.
• Develops and implements strategies, tools, and techniques for RTL development and logic optimization, ensuring designs meet power, performance, area, and timing targets, as well as physical design integrity.
• Possesses a comprehensive understanding of both front-end and back-end flows, with a proven track record of delivering solutions across multiple domains.
• Collaborates effectively with architecture, backend, and other design teams to deliver industry-leading products.
• Builds and sustains a high-performing, technically strong organization by fostering and upholding core group values, norms, and behaviors.
Behavioral traits that we are looking for:
• Excellent in problem-solving, analytical skills.
• Excellent written and verbal communication skills
• Ability to work effectively in a fast-paced environment and collaborative environment
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Education Requirement:
• Bachelor's degree in Computer Science, Electrical, Electronics, Engineering, or related field with 12 years of work experience OR
• Master's degree in Computer Science, Electrical, Electronics, Engineering, or related field with 10 years of work experience OR
• PhD in Computer Science, Electrical, Electronics, Engineering, or related field with 6 years of work experience
Minimum Required Qualifications:
• 6 years of experience in silicon development in the areas of CPU or logic design.
• 5 years of experience in technical leadership and in delivering successful IP Projects.
Additional Preferred Qualifications:
• Experience on x86 CPU microarchitecture
• Experience with driving front end methodologies and championing the use of automation / AI tools to realize tangible benefits visible at the product level.
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Texas, Austin
Additional Locations:
US, Arizona, Phoenix, US, Oregon, Hillsboro
Business group:
Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonus ... (truncated, view full listing at source)
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