Package Design Rule Owner (DRO)
IntelUS, Arizona, Phoenix$142k – $269kPosted 27 March 2026
Job Description
Job Details:
Job Description:
The Role and Impact:
Intel Foundry Technology Development is seeking an experienced Package Design Rule Owner (DRO) to join our Advanced Design and Customer Enabling (ADCE) Package team to support a broad range of product families.
Key Responsibilities:
In this role, your responsibilities will include but not be limited to:
The Package Substrate Design Rule Owner (DRO) is responsible for definition, validation and deployment of design rules for package substrate design. The DRO collaborates with product design, substrate manufacturing and package assembly to identify and drive design rules that enable competitive product designs that meet cost and manufacturability requirements. A key part of this role is being involved from the earliest stages of technology and product concept through to product design tape out. The DRO works across product families to drive a consistent Design Rule strategy and a forward-looking, industry-leading Design Rule roadmap. This position involves working with cross-disciplinary and cross-organizational stakeholders and interfacing directly with product designers. Interaction with external suppliers and customers can also be expected in this role.
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
US Citizenship is required.
Ability to obtain and maintain a US Government TS/SCI Security Clearance with Polygraph.
Bachelor's degree in Electrical Engineering, Chemical Engineering, Mechanical Engineering, Physics, Material Science, or a related STEM field.
6 years of experience with a Bachelor's degree, 4 years with a Master's degree, or 2 years with a PhD.
2 years in semiconductor fabrication processes and packaging technologies.
2 years of experience in package substrate physical design, or thermo-mechanical and electrical performance, or substrate manufacturing and assembly process or a combination of these areas.
Preferred Qualifications:
Active US Government TS/SCI Security Clearance with Polygraph.
Expertise in advanced packaging architectures such as EMIB and Foveros.
5 years of strong analytical and problem-solving skills: identifying, isolating, and debugging issues and providing creative solutions. Ability to work independently and at various levels of abstraction
5 years of strong organization, time management, and communication skills and self-motivated individual.
Good understanding of IC Packaging
Strong Communication skills and the ability to work with others
Take the next step in your career and contribute to Intel's mission of delivering innovative semiconductor solutions that push the boundaries of technology. Apply today to be part of a dynamic team shaping the industry's future.
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Arizona, Phoenix
Additional Locations:
Business group:
Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, reli ... (truncated, view full listing at source)
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