Memory Circuit Design Engineer

Job Details: Job Description: You will be partnering with and leveraging domain experts across various areas of technology development, EDA vendors and product design teams to develop and deliver high-quality industry-leading memory technology collaterals and to drive circuit innovations that enable next generation high-performance, high-density, low-power embedded memory designs on Intel advanced CMOS process technologies. In this position your responsibilities will include, but may not be limited to: Memory pathfinding activities and power, performance and area (PPA) optimization through design technology co-optimization (DTCO) and product design enablement. Memory bit-cell and complex periphery IC layout and automation. Memory array/IP design, memory circuit innovation, test-chip design. Pre-Si verification, post-Si validation and debugging to enable yield and parametric tracking/ramp. The Advanced Design (AD) team is part of Intel's larger Design Technology Platform (DTP) Organization and is focused on pathfinding and development of advanced memory technology. These circuits enable best-in-class memory collateral, IP and innovative product design across all generations of Intel process technology. At Intel, DTP is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable Intel's internal and external customers to get to the market faster with products that include high-performance, high-density, low-power memory at the leading edge of the technology curve and implemented in Intel's advanced CMOS process technologies. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Minimum Qualifications: Education level: Master's degree OR Ph.D. in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related discipline, including 2 years of professional experience. Technical Experience: Experience with CMOS ASIC design flow. Custom digital circuit design, simulation, layout design, and verification Experience with EDA tools used for analog, digital and mixed-signal circuit design. Post-Si validation experience Preferred Qualifications: Master's degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related discipline with 4 years of experience OR Ph. D with 1-2 years of professional experience gained through either internships or full-time employment Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM Design trade-offs between power, performance, and area (PPA) Design technology co-optimization (DTCO) Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations: US, California, Santa Clara Business group: Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth. Posting Statement: All qualified applicants will re ... (truncated, view full listing at source)