Senior Packaging Process Development Engineer

Intel
US, Arizona, Phoenix$164k – $232kPosted 27 March 2026

Tech Stack

Job Description

Job Details: Job Description: The Role and Impact As a Senior Packaging Process Development Engineer ,  you will play a pivotal role in shaping Intel's product packaging solutions to ensure the safe and efficient transport, display, and delivery of Intel products worldwide. Your expertise will drive innovation and sustainability in packaging design, enabling Intel to meet business objectives while exceeding customer expectations. Collaborating with cross-functional teams, you will contribute directly to Intel's success, enabling seamless product launches, improving packaging supply chains, and influencing sustainability practices. This position offers the opportunity to leave a lasting impact on Intel's product distribution channels while aligning with Intel's vision of excellence in engineering and environmental responsibility. Key Responsibilities will include but are not limited to: Design, develop, and qualify packaging solutions and materials that meet product and regulatory requirements. Lead packaging development processes, including artwork creation, concepts, prototypes, qualification testing, and specification documentation. Collaborate with manufacturing, logistics, regulatory, and supply chain partners to ensure packaging solutions meet operational needs. Identify and implement cost-saving, waste-reduction, and efficiency improvement measures for packaging processes. Conduct risk analysis to ensure packaging solutions comply with regulations and align with Intel's quality standards. Consult with cross-organizational teams on branding, marketing, SKUs, labeling, and bills of material requirements for shipments into Intel's distribution channel. Evaluate and qualify vendors to ensure high-quality packaging manufacturing startup and scalability. Benchmark packaging designs and processes against industry standards to maintain a competitive edge. Document and maintain technical specifications for packaging solutions to ensure consistency and clarity. Behavioral traits that we are looking for: Effective communication skills to collaborate with cross-organizational teams and external vendors and customers. Experience leading technical teams, influencing stakeholders, and managing resources and timelines in a matrixed environment. A track record of delivering results in time-critical technical projects involving innovation and strategic planning. Apply problem-solving techniques and fundamental engineering concepts to create novel, efficient solutions. Strong data analysis skills Intel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life. See  Intel Benefits  for more details. Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Note: For information on Intel’s immigration sponsorship guidelines, please see Intel U.S. Immigration Sponsorship Information Minimum Qualifications and Experience : Possess a Master's degree in Engineering, Physics, Chemistry, or a related STEM field with 4 years of educational or work experience. Or a PhD degree in the same fields with 2 years of experience. Your experience describe above must be in the following: Product packaging assembly processes and production methodologies. Statistical process control (SPC) principles and design of experiments (DOE) techniques. Analytical skills with proficiency in data analysis and risk assessment methods. Design for manufacturing (DFM) practices and packaging test criteria. Preferred Qualifications and Experience : Prior experience with Solder joint quality assessment. Experience with Surface Mount Technologies, solder joint formation/quality/reliability, and package certification methodologies . We are looking for individuals who are passionate a ... (truncated, view full listing at source)
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