Packaging Process Development Engineer

Intel
US, Arizona, Phoenix$142k – $200kPosted 27 March 2026

Tech Stack

Job Description

Job Details: Job Description: The Role and Impact As a Product Packaging Development Engineer , you will play a pivotal role in shaping Intel's advanced packaging solutions that directly impact the delivery, performance, and sustainability of cutting-edge products. By applying scientific and engineering principles, you will design and develop innovative packaging solutions that ensure the secure transportation and optimal performance of Intel's products globally. Joining Intel means contributing to groundbreaking projects, collaborating with industry-leading teams, and driving advancements that align with Intel's mission to deliver world-class technology solutions. This role will empower you to influence manufacturing processes, enhance efficiency, and support Intel's growth in the competitive semiconductor industry. Key Responsibilities will include but are not limited to: Design, develop, and qualify packaging solutions and materials that meet product and regulatory requirements. Lead packaging development processes, including artwork creation, concepts, prototypes, qualification testing, and specification documentation. Collaborate with manufacturing, logistics, regulatory, and supply chain partners to ensure packaging solutions meet operational needs. Identify and implement cost-saving, waste-reduction, and efficiency improvement measures for packaging processes. Conduct risk analysis to ensure packaging solutions comply with regulations and align with Intel's quality standards. Consult with cross-organizational teams on branding, marketing, SKUs, labeling, and bills of material requirements for shipments into Intel's distribution channel. Evaluate and qualify vendors to ensure high-quality packaging manufacturing startup and scalability. Benchmark packaging designs and processes against industry standards to maintain a competitive edge. Document and maintain technical specifications for packaging solutions to ensure consistency and clarity. Behavioral traits that we are looking for: Strong problem‑solving skills. Ability to collaborate with engineers across multiple teams. Ability to multitask and work through ambiguity. Clear, concise communication in both written and verbal form. Intel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life. See  Intel Benefits  for more details. Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research, and relevant previous job and/or internship experience. Note: For information on Intel’s immigration sponsorship guidelines, please see Intel U.S. Immigration Sponsorship Information Minimum Qualifications and Experience : Possess a Master's degree in Engineering, Physics, Chemistry, or a related STEM field with 1 years of educational or work experience. Or a PhD degree in the same fields with 6 months of educational or work experience. Your experience described above must be in the following: Product packaging assembly processes and production methodologies. Statistical process control (SPC) principles and design of experiments (DOE) techniques. Analytical skills with proficiency in data analysis and risk assessment methods. Design for manufacturing (DFM) practices and packaging test criteria. Preferred Qualifications and Experience : Experience with Surface Mount Technologies, solder joint formation/quality/reliability, and package certification methodologies. Experience leading technical teams, influencing stakeholders, and managing resources and timelines in a matrixed environment. Familiarity with semiconductor device fabrication processes and pack ... (truncated, view full listing at source)
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