Module Development Engineer

Intel
US, Oregon, Hillsboro$134k – $189kPosted 27 March 2026

Tech Stack

Job Description

Job Details: Job Description: Join Intel - and build a better tomorrow. Intel is in the midst of an exciting transformation, with a vision to create and extend computing technology to connect and enrich the lives of every person on Earth. Join us and help us create the next generation of technologies that will shape the future for decades to come. Engineers within Intel's Logic Technology Development (LTD) organization are chartered with continuing to meet the challenge of Moore's Law in the 21st century. We innovate leading edge fabrication processes and continue to overcome seemingly impossible barriers as tolerances and specifications for building best-in-class computing devices become increasingly rigorous. The role of a Chemical Mechanical Planarization (CMP) Process Development Engineer in LTD encompasses developing and sustaining planarization techniques for a variety of materials and architectures, enabling rapid miniaturization in the semiconductor industry and the mass production of integrated circuits. CMP techniques leverage physics, chemistry, materials science and surface science concepts, and exist at the intersection of these disciplines. As a result, our team has a diverse set of scientific backgrounds that relies on strong collaboration and shared learning. The role’s responsibilities include, but are not limited to: Drives technology development and enablement for both high volume manufacturing and future technology, provides process integration and equipment solutions, and performs feasibility studies to meet desired device specifications. Leads design and development of technically sophisticated manufacturing processes and/or repair reverse engineering including material selection, parameter optimization, equipment metrology, and system design to enable new product designs and functional requirements. Performs pathfinding activities in support of process and hardware development enabling manufacturing of innovative device architectures and develops roadmaps for technologies enabling future roadmap. Recommends and implements modifications for operating equipment to improve production efficiency, manufacturing techniques, and optimizing production output for existing products. Partners with key equipment and materials suppliers to develop and implement enabling elements of the technology. Performs process technology feasibility studies through theoretical simulations and/or practical engineering methods. Remains updated on relevant industrial process and material manufacturing technical trends and develops view of inherent future Intel process technology needs to push industry forward by partnering with vendor ecosystem to build cost sensitive roadmap. Qualifications: You must possess the minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Minimum Qualifications: PhD degree in Electrical Engineering, Electrical Computer Engineering, Chemical Engineering, Material Science, Physics, Chemistry, Computer Science, or a Semiconductor-related STEM (Science Technology Engineering Math) field of study (with a focus on hands-on experimental research). Must be able to start within 12 months. Preferred Qualifications: Statistics Coursework, Statistical Process Control (SPC) or Design of Experiments (DOE) principles, and engineering analysis tools Experimental lab work Semiconductor and transistor device physics Advanced transistor device structures and architectures including fabrication (e.g., lithography, etch, film deposition, cleans, chemical-mechanical planarization, etc.) with in-depth knowledge of semiconductor device physics and process integration Data analysis skills with demonstrated ab ... (truncated, view full listing at source)
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