Analog and Mixed Signal Design Engineer
Intel2 Locations$164k – $269kPosted 27 March 2026
Job Description
Job Details:
Job Description:
The Group: Intel's Advanced Design Foundational IP Organization (AD-FIP) within Design Technology Platform (DTP) focuses on pathfinding and development of advanced logic, memory, and analog/mixed-signal circuits to enable best-in-class Foundational IP collateral and product design across all generations of Intel process technology. Critical technologies AD-FIP delivers to Intel are Digital and Analog Standard Cell Libraries, Embedded Memory (SRAM, RF, ROM, eDRAM, Fuse, etc.), Analog Circuit Reference Designs (PLL, BGR, ADC, etc.), High-speed I/O Reference Designs (DDR, UCIe, PCIe, SerDes, GPIO), RF and Wireless Circuits (Wave Guide TX, Power Amplifier).
As an analog and mixed-signal IC designer your day-to-day responsibilities will include, but not always be limited to:
Developing, designing and testing circuit blocks including wireline IO AFEs, clocking circuits, and voltage regulator circuits as well as integrating them into Intel's leading technology test chips.
Capture of design and measurement results to guide the next generation of process technology and circuit specifications based on requirements for SoC building blocks and critical wireline interfaces.
Work closely with process and IP engineers to anticipate AMS IP requirements and use design and test results to inform and accelerate process technology and product development.
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Bachelor’s degree in Electrical, Computer or Electrical and Computer Engineering, or related STEM field with 10 years of experience, OR
Master's degree in Electrical, Computer or Electrical and Computer Engineering, or related STEM field with 8 years of experience, OR
Ph.D. in Electrical, Computer or Electrical and Computer Engineering, or related STEM field with 3 years of experience.
The qualifications listed below must meet the required years of experience associated with the candidate’s degree level:
Experience with design of custom analog or mixed-signal circuits.
Analog or mixed signal design skills including specification, design or verification.
Preferred Qualifications:
Experience in one or more of the following areas is preferred:
GPIOs, high speed parallel or serial IO links and their subcomponents (data path, TX, RX, etc.), clock distribution, clock conditioning, clock recovery circuits, voltage regulators, voltage reference circuits, ADCs/DACs, inductors, transmission lines, RF and millimeter-wave circuits, test of custom analog and mixed-signal circuits.
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
US, California, Santa Clara
Business group:
Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, mar ... (truncated, view full listing at source)
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