Advanced Packaging TD Plating Module Engineer
IntelUS, Oregon, Hillsboro$156k – $220kPosted 27 March 2026
Job Description
Job Details:
Job Description:
As a Module Development Engineer, you will be at the forefront of Intel's advanced packaging technology development, driving both high-volume manufacturing and the enablement of future technologies. In this role, you will lead the plating process development, optimize equipment solutions, material & chemical selection, and perform feasibility studies to meet device specifications. Your work will directly contribute to Intel's innovation in technology roadmaps, enabling cutting-edge device architecture and advancing semiconductor manufacturing capabilities. By collaborating with cross-functional teams and external suppliers, you will ensure the creation of robust, scalable solutions that position Intel as a leader in the semiconductor industry.
The primary responsibilities for this role will include, but are not limited to:
Drive technology development and enablement for current and future nodes for electroplating needs.
Lead and drive advanced manufacturing processes, including material selection, parameter optimization, equipment metrology, and system design.
Design, execute and analyze experiments to improve electroplating process.
Develop technology roadmaps to guide future manufacturing needs and push industry standards forward.
Collaborate with equipment and material suppliers to design and implement innovative process technologies.
Closely engage with equipment and chem suppliers for better process outcomes.
Optimize production efficiency and manufacturing techniques, while improving output for existing products.
Utilize data analytics and statistical methods to provide insights for continuous process improvements.
Identify and implement modifications for equipments to enhance operational efficiency.
Lead path-finding activities and innovative process development to enable new device architectures.
Qualifications:
Minimum Qualifications :
Minimum qualifications are required to be initially considered for this position.
Master’s degree with 6 years of relevant experience, or PhD with 4 years of experience in Materials Science, Mechanical Engineering, Electrical Engineering, Chemical Engineering, Chemistry, Physics, or a related STEM discipline.
3 years of experience in Electrochemical Plating processing, fab process development, and/or advanced packaging technology.
Advanced knowledge in process development methodology, statistical process control, research and development, and manufacturing process improvement.
Preferred Qualifications:
Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Experience in advanced packaging, RDL-based packaging, or ultra-fine pitch solder connections.
Proven track record in leading programs from strategy formation through high-volume production and sustaining.
Recognized technical leadership and capability to develop solutions to complex engineering problems.
Strong collaboration skills with decision-makers across various functional areas such as yield and operations.
We are looking for innovative and disciplined individuals passionate about advancing semiconductor technology. Apply today to become part of Intel's mission to shape the future of technology.
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
Business group:
Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. E ... (truncated, view full listing at source)
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