Atom CPU Layout Design Intern

Job Details: Job Description: This position requires candidates to upload a resume in English; you are welcome to upload multiple versions of your resume if you prefer but an English version of your resume will be required to be considered for this position. As an Atom CPU Layout Design Intern, you will be part of a high‑impact engineering team contributing to the development of next‑generation, high‑performance Intel Atom microprocessors. In this role, you will support the physical implementation of memory compilers, custom IP blocks, and CPU partitions. You will work on assignments that are complex, non‑standard, and require strong technical judgment within broadly defined design parameters. Key Responsibilities Execute physical layout design tasks while ensuring adherence to best ‑ in ‑ class design practices and efficiency standards. Independently assess, plan, and drive complex physical design assignments from definition through completion. Collaborate with senior engineers to develop layout methodologies, automation scripts, and custom macros (experience or interest in scripting is a plus). Behavioral Traits Problem ‑ Solving Mindset: Approaches complex technical challenges with curiosity, creativity, and structured analytical thinking. Attention to Detail: Ability to identify errors, inconsistencies, and opportunities for optimization in layout work. High Learning: Willingness to quickly absorb new technical concepts and apply them to real design challenges. Team Collaboration: Comfortable working with cross-disciplinary engineering teams and contributing to shared goals. Proactive Mindset: Takes initiative to propose ideas, ask questions, and seek continuous improvement. Adaptability: Able to manage changing priorities and work effectively on nonstandard, complex assignments. What You Will Learn During this internship, you will gain hands ‑ on experience with: Advanced VLSI layout methodologies used in modern CPU development. Physical implementation flows, including floorplanning, routing, design rule checks (DRC), and layout vs. schematic verification (LVS). EDA tools and automation, learning how to optimize layout productivity and quality through scripting and custom methodologies. Microprocessor architecture fundamentals and how physical design impacts power, performance, and area (PPA). Cross-functional engineering collaboration, working directly with design, architecture, and verification teams. This internship provides exposure to real product development cycles and prepares students for full ‑ time roles in physical design, CPU design, or custom circuit layout. Qualifications: Minimum qualifications are required to be initially considered for this position.  Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Minimum Qualifications: Pursuing a Bachelor's or Master degree in Electrical Engineering, Computer Engineering, Computer Science, or a STEM related field. Advance English level. Must have unrestricted, permanent right to work in Mexico (this role is not eligible for visa or immigration sponsorship). Preferred Qualifications: 3 months Coursework, Internship and/or experience in any of the following areas: Familiarity with n VLSI and CMOS logic circuit design Knowledge in Unix/Linux operating systems A candidate who accepts an offer of employment in Mexico is required to present their own personal identification information and numbers for the following: Mexican Security Number (NSS), Tax Identification Number (RFC) and CURP identification number. Job Type: Student / Intern Shift: Shift 1 (Mexico) Primary Location: Mexico, Guadalajara Additional Locations: Business group: Silicon and Platform Engineering Group (SPE): Deliver breakthrough ... (truncated, view full listing at source)