Shift 4 Module Engineer On Shift (MEOS)

Intel
US, Arizona, Phoenix$99k – $163kPosted 27 March 2026

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Job Description

Job Details: Job Description: Become a part of Intel's Advance Packaging Team by joining the Substrate Packaging Technology Development (SPTD) organization. Our mission is to be the supplier of choice for leading and affordable substrate packaging. Join the SPTD organization to assist in achieving our mission and continuing to make this a great place to work. The role of a Module Engineer On Shift (MEOS) is to provide factory support by handling equipment, process and product issues in real-time to facilitate 24x7 lot movement through the manufacturing line. MEOS responds to process issues, error recovery, lot disposition, new tool enabling and many ad-hoc duties in specific functional area that the factory may require. Shift Hours: Employees working in Shift 4 start their shift at 6:00 PM and finish at 6:00 AM Alternating Work Weeks: Alternating 3 and 4 Day Work Week (Sunday through Tuesday and alternating Saturday) Your role and responsibilities include (but are not limited to): Receiving both written and verbal pass down from leaving shift peers Aligning on priorities with management Majority of shift is in the factory supporting tool and process issues; Writing/Updating Specs and RFCs as needed Executing non-standard procedures and performs Inspection and imaging on panels to get development data Communicate by email with Tool/Lot Owners for key issues Provide a quality pass down of all shift activities to on-coming shift both written and verbal Aside from the qualifications provided below, the ideal candidate shall possess the following behavioral traits: Problem-solving and troubleshooting skills Verbal and/or written communication skills with the willingness to effectively communicate with peers, engineers and customers Flexibility and efficiency of handling new tasks Willingness to work with minimal supervision and adjust to rapidly changing priorities Be a self-starter capable of managing own activities as well as supporting team activities Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Bachelor's degree in any of these engineering disciplines: Materials Engineering/Mechanical Engineering/Chemical Engineering/Chemistry/Physics or related discipline with 1years of relevant experience OR Master's degree in any of these engineering disciplines Materials Engineering/Mechanical Engineering/Chemical Engineering/Chemistry/Physics or related discipline Preferred Qualifications: 1 years of experience in statistical process control (SPC), Metrology tool recipe creation and tool troubleshooting 1 years of experience in Semiconductor Packaging or Packaging substrate manufacturing Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. For information on Intel’s immigration sponsorship guidelines, please see Intel U.S. Immigration Sponsorship Information Job Type: Experienced Hire Shift: Shift 4 (United States of America) Primary Location: US, Arizona, Phoenix Additional Locations: Business group: Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and asse ... (truncated, view full listing at source)
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