Principal Engineer, Design Technology Co-optimization

Job Details: Job Description: Organization Description Advanced Design & Foundational IP (ADFIP) is part of Design Technology Platform (DTP) under Foundry Technology Development. ADFIP's core focus is design-technology co-optimization (DTCO), system-design co-optimization (STCO) and foundational IP development to support Intel technology development, internal client/server/NEX products and external tie0/tie1 customers. The organization develops logic libraries, memories, high-speed I/Os, analog and mixed signal IPs, RF/mmWave circuits and 3D IC, and conducts comprehensive Si validation on process and package development test vehicles and FIP characterization vehicles. Advanced power, performance and area (PPA) analysis is conducted across domains to guide silicon and packaging technology definition to maximize technology PPA entitlement and minimize process risks and cost. Job Role & Responsibility Description As a logic library vertical lead, you will be responsible for driving optimization of standard cell libraries on Intel's leading edge process nodes to meet internal and external foundry customer needs. You will directly interface with key Intel foundry customers to understand technology and library gaps and drive co-optimization with Intel foundry technology development teams and EDA partners. Your responsibility includes optimizing library circuits in close collaboration with physical design engineers to provide optimally tuned layout to improve cell performance, power and area, collaborating with EDA partners to optimize cell content in standard cell library to improve Intel technology entitlement at product level. Required Skills and Experience Strong technical understanding of advanced semiconductor technology Strong technical understanding of foundation IP design and design-technology co-optimization Experience in standard cell library design with good understanding of MOSFET electrical characteristics, local layout effects, variability at advanced nodes Experience with library cell characterization methodology and tools and Spice circuit simulations Experience in semiconductor foundry ecosystem from foundry, EDA/IP, or foundry customer perspective Excellent oral and written communication skills Collaborative mindset and great team player Good track record of technical leadership and delivery Preferred Skills and Experience Experience in product designs with good understanding of signoff methodology, tradeoffs across power, performance and tradeoff Familiar with pre and post Si foundry benchmarking practices Familiar with EDA tool design and optimization with experience in identification, design and verification of cells targeted to improve product level PPA Experience in foundation IP Si validation Qualifications: Ph.D. or master's degree in electrical engineering or computer science 10 years of industry experience Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations: US, Arizona, Phoenix, US, California, Santa Clara, US, Texas, Austin Business group: Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth. Posting Statement: All qualified applicants will receive consideration for employment without r ... (truncated, view full listing at source)