Post-silicon Validation and Debug Engineer

Job Details: Job Description: The Role and Impact As a SoC Debug Engineer, you will play a pivotal role in ensuring Intel's cutting-edge products perform seamlessly, innovating at the intersection of hardware, firmware, and software. Join our team to shape the future of technology by driving exceptional system-on-chip (SoC) debug solutions, improving industry workflows, and defining strategies that contribute to Intel's global leadership in innovation. This position offers an exciting opportunity to collaborate with cross-disciplinary teams, influence technical direction across Intel, and develop solutions fundamental to delivering high-quality products to market. Key Responsibilities Perform low-level and complex debug across multiple systems, subsystems, or SoC levels for Intel products. Develop validation plans and execute tests for multiple domain- and system-level features/flows in the SoC. Develop and implement techniques for faster SoC and platform-level debug while isolating failing system components. Utilize design-for-debug (DFD) tools and scripts to continuously improve debug discipline. Conduct root cause analysis, resolve triage failures and marginality issues, and track SoC debug progress. Collaborate with design, system validation teams, and high-volume manufacturing factories to characterize new device features and functionalities. Qualifications: Minimum Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. 0-1 years of experience with a Bachelor's degree or 0 years with a Master's degree in SoC design and debug or equivalent experience. Proficiency in SoC design, architecture, and debug techniques, including DFD tools and methodologies. Strong understanding of firmware and software integration in hardware systems. Ability to apply debug workflows using advanced test methodologies and failure isolation techniques. Preferred Qualifications Master's degree in Electrical Engineering, Computer Engineering, or related disciplines. Exposure to collaborating across design and validation teams to achieve debug readiness. Familiarity with Graphics and Power Management flows in an SoC design. Drive to influence technical strategies and align organizational goals with technical vision. Job Type: College Grad Shift: Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations: US, California, Folsom Business group: Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel . Annual Salary Range for jobs which could be performed in the US: $105,650.00-149,150.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will require an on-site pr ... (truncated, view full listing at source)