SoC/IP Design Verification Engineer

Job Details: Job Description: We're looking for a hands-on SoC Design Verification Engineer to drive verification for complex SoC/IP blocks. You will own verification planning, UVM testbench development, test content creation (directed and constrained-random), coverage closure, and debug across block, subsystem, and SoC levels. You'll collaborate closely with design, architecture, firmware, and validation teams to deliver high-quality silicon on schedule. What You'll Do (Key Responsibilities) • Own the verification lifecycle for one or more IPs/subsystems/SoC top-level features: requirements decomposition, test plan definition, coverage strategy, execution, and signoff. • Architect and implement UVM environments (agents, drivers, monitors, sequencers, scoreboards, reference models), with scalable, reusable components. • Develop test content: constrained-random sequences, scenario tests, stimulus libraries, checkers, and assertions. • Debug failures quickly and methodically across simulation and emulation (waveforms, logs, assertions, checkers, reference model mismatches). • Drive coverage closure (functional and code coverage): define, measure, analyze holes, and implement closure strategies. • Leverage assertions (SVA) and formal where appropriate to strengthen verification quality and accelerate bug find. • Integrate VIPs (e.g., AXI/ACE/PCIe/DDR) and coordinate with external/internal IP teams for models, checkers, and coverage. • Collaborate cross-functionally with RTL design, architecture, DV, DFT, performance, firmware, and post-silicon validation to ensure feature completeness and testability. • Continuously improve flows: contribute to methodology, regressions, CI/CD, and verification infrastructure (e.g., Makefiles, Python utilities, farm scripts). • Document plans, environments, and results; present status, risks, and signoff evidence to stakeholders. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimun Qualification • BS/MS in Electrical/Computer Engineering or related field (or equivalent practical experience). • 5 years of SoC/IP design verification experience • Strong UVM/SystemVerilog development expertise (testbenches, agents, scoreboards, virtual sequences, factory/objection/callback mechanisms). • Test planning experience: translating architectural/RTL specs into measurable, coverage-driven verification plans. • Proven debug skills in simulation/emulation (e.g., Synopsys VCS, Cadence Xcelium, Siemens Questa; waveform tools like Verdi/DVE/SimVision). • Coverage-driven verification: functional coverage modeling, code coverage analysis, coverage closure workflows. • Scripting proficiency (Python, Perl, Shell, Make/CMake) for automation, regressions, and data analysis. • Excellent communication and collaboration; ability to deliver in fast-paced, multi-site environments. Preferred Qualifications: • SoC-level verification experience: fabric/interconnect, security, • Experience with standard protocols: AXI/ACE/CHI, PCIe, LP/DDR, USB, MIPI, I3C, SPI/I2C, Ethernet; integrating and customizing VIP. • Assertion-based verification (SVA) and formal (JasperGold/VC Formal/PropCheck) for property checking and bug hunting. • Power-aware verification (UPF/CPF), isolation/retention, multi-voltage domains. • Emulation/FPGA prototyping (Palladium, Zebu, Veloce), transaction-level acceleration, hybrid verification. • Performance/latency/throughput test content and checkers; scoreboard/reference model design for complex data paths. • Exposure to C/C/SystemC reference models or firmware-aware verification. • Experience leading small teams, mentoring, or driving signoff for a tapeout. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job T ... (truncated, view full listing at source)