Standard Cell Design Reliability Verification Engineer

Job Details: Job Description: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Candidate must have a Master's degree with 5 years of relevant industry experience or PhD degree with 1 years of relevant industry experience in the field of Electronics, Electrical and/or Computer Engineering or related fields with specialization in VLSI and knowledge in: - Extensive experience in all aspects of the IR and EM flows for Standard cells at device level and ASIC designs. - In depth understanding of EM and IR flows methodologies using Synopsys Primelib RV, PrimesimEMIR, PrimesimXA RV, Ansys RHSC and Cadence Voltus tools with associated Process Design Kit collaterals dependency. - Expertise with Reliability verification in lower nm nodes and EM/IR concepts with a proven track record in establishing RV flows, debug problems and drive solutions working with cross functional teams and EDA vendors. - Digital circuit design, including CMOS combinatorial logic and sequential element design and layout. - Strong understanding of device physics, FinFet characteristics and Standard Cell Library design. - Strong Python programming and automation skills. - Excellent understanding of various Standard Cell Library collaterals and PV Timing Analysis. - Good understanding of a) Development of automation for library modeling, validation, quality checking, performance, and reliability verification b) Standard library release build, validation, QA, release, and support c) Technically lead a team of engineers, debug problems, remove execution roadblocks, detailed planning of execution/releases, and work on strategic initiatives for future technologies d) Parasitic extraction and circuit optimization for power/performance/robustness/density. - Excellent collaboration skills across geographically distributed teams and being able to handle ambiguity while developing expertise in new areas and delivering excellent, quantifiable results will be key to the success in this role. The successful candidate must possess excellent written and verbal communication skills, strong customer/result orientation and the ability to work with external, internal partners and with EDA vendors in a flexible manner. Preferred Qualifications: Experience with Industry standard tools - Synopsys Primelib RV, PrimesimEMIR, PrimesimXA RV, Ansys RHSC, Cadence Voltus, Design Compiler, Genus, Tempus, ICV Experience in digital circuit design, front end model creation and functional verification. Experience with standard cell library characterization, thermal models, emt models, liberty models and cross validations with front end models and liberty models. Industry Experience on Reliability verification of standard cells covering ERC, EM, SH, FinFet self-heating. Experience working with EDA vendors to drive new features and capabilities. Knowledge of industry-standard EDA tools for VLSI circuit and layout design. Experience working in the Linux environment and its development tools. Standard cell level PPA modeling, simulation, and ROI analysis. Experience in CMOS power modeling and cell level optimization. CMOS and standard cell level device variation and Aging analysis. Engineering acumen and analytical skills. Debugging skills. Customer oriented and able to work in a dynamic environment. Requirements listed would be obtained through a combination of industry relevant job experience, and or schoolwork/classes/research Qualifications: Design Technology Platform (DTP) organization, collaborating closely with partners in process technology, IP, and products spanning client/server and networking products. The primary focus of AD-FIP is to guide process technology definition, design prototypes in Intel's latest process technology, develop Foundational IP's supporting Intel's internal and external design ... (truncated, view full listing at source)