ASIC Engineer

Job Title: ASIC Engineer Location: San Jose, CA Duration: 6 Months Minimum Required Skills: ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation,Synthesis /Conformal (Cadence Tool for formal verification) Description: Should have 2-5 years of experience in FPGA/ASIC Development Build RTL designs of digital circuits using VHDL and System Verilog Perform frontend design development and integration of large ASIC designs Collaborate with Chip Architecture, Design Verification, and Physical Design teams to achieve first tapeout success. Write design documents including high level interface descriptions and design descriptions. Write function test cases and test benches to verify functionality of designs Team work and proactive sharing of knowledge Comfortable working in a fast paced environment. ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation,Synthesis /Conformal (Cadence Tool for formal verification) All your information will be kept confidential according to EEO guidelines.