HW Post-Silicon Validation Engineer
CiscoSan Jose, California, US$153k – $219kPosted 8 May 2026
Job Description
The application window is expected to close on: 05/08/2026
Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received .
Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.
Meet the team:
Welcome to the Post-Silicon Validation Team at Cisco! Our group offers a unique combination of a startup culture with the benefits of working for the leading networking company in the world. You will engage in dynamic collaboration with verification engineers, designers, and cross-functional teams, working together to ensure the successful verification of the ASIC throughout its lifecycle.
Operating at the forefront of technology, we work with cutting-edge, high-speed, and power-hungry devices. Our small, but highly influential team thrives in this challenging environment, leveraging our expertise to impact the future of networking technology. With a commitment to excellence and a passion transformative technology, we are shaping the future of high-performance Networking and delivering unparalleled value in every project we undertake. Join us and be a part of a team where professionalism meets impact
Your Impact:
We are seeking a Post-Silicon Validation Engineer with a strong interest in hands-on, lab-intensive hardware validation to support testing and debug of networking silicon. This role is heavily focused on working in silicon validation labs, bringing up new hardware, performing detailed electrical and protocol measurements, and owning root-cause analysis of silicon and board-level issues. The position offers extensive exposure to networking silicon, high-speed interfaces, and cross-functional team collaboration.
Key Responsibilities
Perform hands-on post-silicon electrical validation in lab environments for networking ASICs, and evaluation platforms
Support early-silicon bring-up activities
Execute detailed hardware validation plans covering functionality charactarization, performance, and reliability
Set up, configure, and maintain lab benches, boards and test equipment
Assist with power-on, reset sequencing, clock bring-up, and strap configuration
Perform voltage, current, and signal integrity measurements
Capture and analyze waveforms, eye diagrams, jitter, PDN measurements and error metrics
Help isolate silicon, board, or signal integrity issues under guidance
Validate Ethernet MAC/PHY and high-speed interfaces such as PCIe and SerDes
Assist with link training, lane margining, and BER testing
Support packet-level validation using traffic generators and protocol analyzers
Operate oscilloscopes, logic analyzers, VNAs, protocol analyzers, and multimeters
Use lab automation tools and scripts to control equipment and capture data
Use thermal chambers and chillers to perform temperature related tests
Perform minor soldering re-work on test boards.
Follow ESD, safety, and lab best practices at all times
Minimum Qualifications:
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field with a minimum 3 years of experience (internships, co-ops, or academic lab experience acceptable)
Prior experience in electronics, digital logic, and signal integrity concepts
Experience in schematics/Layout files and understand board-level designs
Preferred Qualifications:
Experience with silicon bring-up or hardware validation labs
Experience with: DDR5, USB3.0, SGMII, PCIe Gen3.x, USB2.0, eMMC, SPI, MDIO, I2C, UART.
Exposure to Ethernet, PCIe, or SerDes testing
Experience with high-speed measurement techniques (eye diagrams, BER, jitter)
Experience for lab automation (Python)
Understanding of networking fundamentals and packet-based systems
Why Cisco?
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and te ... (truncated, view full listing at source)
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