ASIC Technical Leader- DFT

The application window is expected to close on: 05/08/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . Meet the Team: You will be in the Silicon One development organization as an ASIC Implementation Technical Lead  with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle.  As a member of this team you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities. Key Contributions: Manages the definition, architecture and design of high performance ASICs Owns applications or multiple complex functional areas Oversees reusable code and its applications Creates re-usable code that promotes efficiencies in new ways Defines verification strategies Coordinates with appropriate stakeholders to integrate into PD and DV flows Owns infrastructure and testing environmens Leads and designs the building blocks of multiple channels Applies and drives the design methodology from conception to production Influences and collaborates with teams to ensure specifications and requirements are met Leads technical expertise of a physical design function Interfaces with vendors and design leads on full chip timing closure, PI, and PV Owns the full electrical planning and specifications of electrical interfaces Develops multiple solutions, first test vehicles and performs verification and validation Minimum Qualifications: Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least 10 years of experience. Prior experience with Jtag protocols ( p1500, p1687) , Scan insertion and BIST architectures, including memory BIST and boundary scan. Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, test static timing analysis constraints development and timing closure. Prior experience working with Gate level simulation, including timing based simulations. Post-silicon validation and debug experience; Ability to work with ATE engineers on pattern translation and validation. Scripting skills: Tcl, Python/Perl. Preferred Qualifications: Verilog design experience – developing custom DFT logic & IP integration; familiarity with functional verification DFT CAD development – Test Architecture, Methodology and Infrastructure Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada: The starting salary range posted for this position is $183,800.00 to $263,600.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits. Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary ... (truncated, view full listing at source)