Memory Design Application Engineer
Intel3 Locations$122k – $232kPosted 7 April 2026
Job Description
Job Details:
Job Description:
About Intel Foundry Services
Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain.
Position Overview
The Aerospace, Defense & Government (ADG) Memory Design Application Engineer provides specialized technical support to Intel Foundry Services customers on memory compiler generation and integration challenges. This critical role ensures successful customer tape-outs by resolving complex memory IP integration issues, driving quality improvements in memory collaterals, and delivering comprehensive technical guidance on memory design methodologies for advanced semiconductor applications.
Key Responsibilities
Memory IP Technical Support & Integration
Provide comprehensive technical support to Intel Foundry Services customers on memory compiler generation and integration issues
Collaborate with internal Intel teams and external stakeholders including foundry customers' design teams, Memory IP providers, and EDA vendors on foundational IP integration issue resolution
Drive resolution of customer issues related to memory IP collaterals, ensuring seamless integration and optimal performance
Technical Content Development & Training
Create application notes, comprehensive documentation, and deliver technical training presentations to customers and internal teams
Drive quality improvements in design kits, Memory IP collaterals, and documentation to remove barriers to successful customer design tape-outs
Develop best practice guidelines for memory integration across advanced process technologies and customer applications
Memory Design Methodology & Problem Solving
Lead debugging and problem-solving activities in collaborative team environments
Provide technical expertise on memory compiler design, generation, and optimization
Support customers through complex memory design challenges and advanced integration requirements
Drive methodology improvements to enhance memory design productivity and reliability
Customer Engagement & Technical Excellence
Deliver customer-facing technical support with focus on memory design and integration solutions
Ensure maximum customer satisfaction through expert guidance on memory IP implementation
Support aerospace, defense, and government customers with specialized memory requirements and security considerations
Core Competencies
Self-driven and results-oriented with capability to effectively manage multiple complex tasks
Effective communicator with strong interpersonal and leadership capabilities, fostering collaboration across cross-functional teams and providing constructive feedback
Qualifications:
The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates
Minimum Qualifications
US Citizenship required
Ability to obtain a US Government Security Clearance
Bachelor's degree in Electrical Engineering, Computer Science, or in a STEM related field of study
3 years of experience with Memory design or Memory Compiler development and implementation
Preferred Qualifications:
Active US Government Security Clearance with a minimum of Secret level
Post Graduate degree in Electrical Engineering, Computer Science, or in a STEM related field of study
Proficient in common memory types, including SRAM, Register Files (RF), and ROM, with a solid unders ... (truncated, view full listing at source)
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