Principal ASIC Design Engineer

Medtronic
Mounds View, Minnesota, United States of America$135k – $203kPosted 7 April 2026

Job Description

We anticipate the application window for this opening will close on - 10 Apr 2026 At Medtronic you can begin a life-long career of exploration and innovation, while helping champion healthcare access and equity for all. You’ll lead with purpose, breaking down barriers to innovation in a more connected, compassionate world. A Day in the Life At Medtronic, our ASICs save lives. This means our designers need to understand the big picture of how their work impacts the end user, a patient. We have an integrated ASIC team enabling engineers to wear many hats from digital design, verification, the physical flow, to testing in the lab with opportunities to meet doctors and witness implants; which connects how our work directly impacts patients' lives. Our group is developing Medtronic's next generation of Cardiac Rhythm Management (CRM) products using innovative low power SoC methods to improve how our implantable devices provide pacing, defibrillation, and monitoring therapies. At Medtronic, we bring bold ideas forward with speed and decisiveness to put patients first in everything we do. In-person exchanges are invaluable to our work. We’re working a minimum of 4 days a week onsite as part of our commitment to fostering a culture of professional growth and cross-functional collaboration as we work together to engineer the extraordinary. This position will be based in Mounds View, MN. Below are the minimum requirements for a principal level position, candidates above or below are encouraged to apply as this role could be reposted to align with a candidate’s experience. As a member of this Design Team, the Principal ASIC Design Engineer can be involved in all phases of product development, including design definition, verification planning / execution, physical implementation, design for testability, system integration, characterization, and failure analysis under a regulated quality and standard operating procedures. You will be an important part of an experienced product development team whose goal is to deliver the highest quality integrated circuits for use in life saving medical devices. For this role we are particularly looking for ASIC engineers interested in supporting both design and physical flow activities with strengths in scripting or DSP development. This strengthens the team’s ability to adapt to shifting project needs and timelines. Role and Responsibilities Create System Verilog RTL designs from product specification to defining architecture, and block level implementation. ASIC physical design implementation: synthesis, Static Timing Analysis (STA), Place and Route (PAR), UPF/CPF Interact with Place and Route, Static Timing Analysis team to drive best implementation for floor planning, clock tree design, timing closure, and low power. Support verification for coverage improvement and design debug. Interact and influence product engineering, test engineering, research and FW teams as part of the product development process. Determines design approaches and parameters. Analyzes ICs using lab equipment to verify functionality and operating range, conducts experimental tests and evaluates results. Must Have: Minimum Requirements for Principal ASIC Design Engineer To be considered for this role, please ensure the minimum requirements are evident in your applicant profile Bachelors degree required Minimum of 7 years of ASIC Design experience Or Masters degree with minimum 5 years of ASIC Design experience Or Phd with 3 years of ASIC Design experience. Nice to Have Medical Device experience preferred Master’s degree in Electrical Engineering/Computer Engineering Strong scripting skills (Python, TcL, Perl…) Universal Verification Methodologies (UVM) Cadence CAD tools:  Genus/Conformal/Innovus/Voltus/Tempus/Modus Lab automation methods Low power design methods and power analysis Digital Signal Processing (DSP) Developing for mixed signal ICs with Digital Analog Boundary (DAB) crossings, A2D, D2A ... (truncated, view full listing at source)
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