High Speed AI Interconnect Signal Integrity Engineer

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a senior High Speed Interconnect / Signal Integrity Engineer to design and validate high-bandwidth links for large-scale AI systems. You will define, model, and qualify interconnect solutions across copper and optical technologies for next-generation AI inference and training clusters. This role is on-site in Santa Clara, CA, Austin, TX, or Toronto, Canada. We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting Who You Are An experienced electrical engineer with a Bachelor’s or Master’s in Electrical Engineering. 5+ years working on high-speed communications (100G–1.6T), including signal integrity, channels, and links. Comfortable building and owning link and channel budgets and making clear tradeoffs between reach, loss, BER, and margin. Hands-on with SI tools and lab equipment such as Keysight ADS, VNAs, TDRs, BERTs, and protocol analyzers. Familiar with cable specification and testing, as well as accelerated life testing, mating life, and failure analysis. Able to collaborate across hardware, systems, and manufacturing teams; manufacturing/DFM/DTM experience is a plus. What We Need Define and specify high-speed interconnect architectures between systems within large AI clusters. Develop requirements, validation plans, and test strategies for passive and active copper cables and optical transceivers at 100G, 400G, 800G, and 1.6T. Document topologies, routing assumptions, and cable requirements for internal and customer-facing clusters. Perform link and channel budget analysis, including loss, jitter, eye margin, and BER considerations across PVT and aging. Lead and execute qualification and reliability testing, including accelerated life testing, mating life, and failure analysis for interconnect components. Interface with key industry suppliers, track their roadmaps, and align Tenstorrent’s system designs to future interconnect capabilities. What You Will Learn How to design and validate interconnects for large-scale AI training and inference clusters, spanning multiple generations of Tenstorrent silicon and systems. Practical methodologies for closing SI margins at cutting-edge speeds (up to 1.6T) across diverse media (backplane, copper cable, optics). How to translate supplier roadmaps and standards into concrete system requirements and deployment constraints for real customer workloads. End-to-end exposure to AI system architecture, from rack-level topology choices down to connector, cable, and transceiver details, in collaboration with world-class AI hardware and systems teams. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transfer ... (truncated, view full listing at source)