Staff Design for Test Engineer

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. The role is Design for Test (DFT) for high-performance designs going into industry leading AI/ML architectures. The person coming into this role will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High level challenges include reducing test cost while attaining high coverage, and facilitating debug and yield learnings while minimizing design intrusions. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC. This role is hybrid, based out of Santa Clara, CA or Austin, TX We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You have a BS/MS/PhD in EE/ECE/CE/CS with 5+ years of industry experience in advanced DFx/DFT for complex ASIC/SoC designs. You are fluent in Verilog RTL for DFT logic (lock-up latches, clock gates, scan anchors) and comfortable with SystemVerilog/UVM. You have hands-on experience with ATPG and DFx insertion tools, fault models (Stuck-at, Transition, Path Delay, IDDQ, Cell-Aware), and low-power design flows. You bring strong debug and problem-solving skills across design hierarchies and collaborate effectively with design, PD, verification, and test teams. What We Need Implement and integrate DFT features (scan, JTAG, compression, ASST, MBIST) into RTL from early design through tapeout across multiple IPs. Own ATPG, test coverage analysis, and gate-level simulation (e.g., with Synopsys VCS/Verdi) to achieve and maintain high-quality test coverage. Plan, implement, and verify MBIST, and work closely with Test Engineering on test planning, pattern delivery, and debug. Develop and refine DFx flows and methodology that integrate cleanly with front-end and physical design flows, balancing coverage, test cost, and design intrusiveness. What You Will Learn How to drive DFT for industry-leading AI/ML architectures, working on high-performance chips with aggressive performance and power targets. Practical strategies to reduce test cost while maintaining coverage, and to design DFT hooks that accelerate silicon bring-up and yield learning. How to minimize DFT intrusions while integrating cleanly with RTL, verification, physical design, and production test flows. How a senior, cross-functional ASIC team collaborates across design, PD, verification, and manufacturing to achieve first-pass silicon success on advanced nodes. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. a ... (truncated, view full listing at source)