SOC Design Verification Engineer

Job Details: Job Description: Role Overview We are seeking a skilled Verification/Validation Engineer with expertise in developing testbenches for pre-silicon verification. The role involves building scalable verification environments, creating stimulus, monitoring functionality, and ensuring coverage closure using industry-standard methodologies. Key Responsibilities Own the verification lifecycle for one or more IPs/subsystems/SoC top-level features: requirements decomposition, test plan definition, coverage strategy, execution, and signoff Develop System Verilog/UVM-based testbenches for IP, subsystem, or SoC-level verification. Create and maintain verification plans, test cases, and coverage models. Implement and integrate scoreboards, monitors, checkers, assertions, and transactors for functional correctness. Work with Verification IP (VIP) for industry-standard protocols (AMBA,AXI, UCIe, PCIe, DDR etc.) and integrate them into testbenches. Build reusable constrained-random and directed test scenarios. Debug failures, perform root cause analysis, and work closely with design and architecture teams. Analyze functional coverage, code coverage, and assertion coverage to ensure verification completeness. Participate in design/verification reviews and contribute to methodology improvements. Automate regression runs and maintain CI verification flows (Jenkins, Git, etc. if applicable). Qualifications: Required Skills & Qualifications Bachelor’s/Master’s in Electrical/Electronics/Computer Engineering or related field with 5 Years of Experience is required. Strong hands-on experience with System Verilog and UVM methodology. Proven experience in transactor modelling and VIP integration/customization. Good understanding of digital design fundamentals (RTL, FSMs, buses, etc.). Familiarity with coverage-driven verification and constraint random test generation. Proficiency with industry-standard simulators and/or emulators (Synopsys VCS/Zebu, Cadence Xcelium/Palladium, Mentor Questa/Veloce, etc.). Debugging skills using waveforms and verification tools. Exposure to SVA (System Verilog Assertions) and functional coverage techniques. Must Have Experience with C/C/Python for testbench integration or automation. Hands-on work with protocol VIPs (AXI, AHB, APB, CXL,UCIe, PCIe, DDR, Ethernet, USB, etc.). Experience in X86/ARM architecture. Strong communication and teamwork skills. Experience in applying AI tools for verification/validation is a plus Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as w ... (truncated, view full listing at source)