Senior DFT Timing Signoff Engineer (STA)

Job Details: Job Description: The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful. The Role: We are seeking a highly skilled and hands-on DFT/STA Engineer to join our full-chip timing organization supporting next-generation AI processors. This is a backend role focused on PrimeTime-based DFT-mode timing constraints, constraints hygiene, and signoff readiness. The role requires deep understanding of Tessent DFT architecture and implementation concepts-including Streaming Scan Network (SSN), IJTAG/test access integration (HTAP, TAPLink), and memory test/repair (MBIST/BISR)-and the ability to translate DFT intent into correct, auditable timing constraints and stable signoff across all DFT modes. You will collaborate closely with DFT architecture/implementation teams, RTL, Physical Design (Synthesis/CTS/PnR), and Product/Test Engineering to enable first-pass silicon success. Key Responsibilities: DFT Timing Constraints and PrimeTime Signoff Ownership Own the definition, generation, validation, and maintenance of comprehensive DFT timing constraints (SDC) in Synopsys PrimeTime for modes including Scan Shift, Scan Capture (slow/fast as applicable), JTAG/IJTAG, and Memory BIST. Own PrimeTime STA signoff for DFT modes at both block and top level across relevant corners and operating conditions; ensure correctness, coverage, and auditable exception governance (false paths, multicycle paths, case analysis). Establish and enforce constraints hygiene standards: mode separation, exception audits, constraint reviews/linting, and regression strategies to prevent drift and late-cycle surprises. Tessent DFT Architecture Collaboration (SSN / IJTAG / HTAP / TAPLink / MBIST) Partner with DFT architecture and implementation teams to support Tessent-based integration, including Streaming Scan Network (SSN) architecture/implementation considerations, IJTAG/test access strategy (HTAP, TAPLink), and MBIST/BISR collateral and constraints needs. Translate DFT architecture intent into timing assumptions and constraints that are signoff-safe, traceable, and robust across integration drops. Debug complex DFT insertion/integration issues (RTL and gate-level netlists) that impact test-mode timing closure and signoff. Backend Closure Execution (PD/CTS/ECO) Drive DFT-mode timing convergence by partnering with Synthesis/CTS/PnR teams to debug complex violations and guide/implement ECO strategies when needed. Develop repeatable signoff checklists and reporting that clearly communicate DFT-mode signoff readiness and risks to stakeholders. Flow Improvement and Automation Improve DFT/STA flows through automation (Tcl required; Python/shell preferred): multi-mode runs, report triage, regression checks, and signoff dashboards. Identify and implement methodology improvements that increase efficiency, reduce churn, and improve confidence in DFT-mode signoff. Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences. Minimum Qualifications: Bachelors & 8 years or Masters & 6 years in Electrical Engineering, Computer Engineering, or related field with 6 yea ... (truncated, view full listing at source)