Silicon Packaging Engineer - Wireless Communications Solutions
IntelUS, Oregon, Hillsboro$142k – $200kPosted 11 April 2026
Tech Stack
Job Description
Job Details:
Job Description:
About This Opportunity
Join Intel's Wireless Communications Solutions (WCS) team during an exciting period of innovation and new development opportunities. WCS focuses on developing advanced wireless technologies and solutions that enable seamless connectivity across a wide range of devices and platforms. The group specializes in wireless communication products including Wi-Fi, Bluetooth, and emerging wireless standards, delivering high-performance, reliable, and secure wireless solutions.
WCS drives innovation in wireless connectivity by integrating cutting-edge hardware and software technologies to meet the evolving needs of consumers and enterprise customers. The business unit ensures regulatory compliance and quality through rigorous product regulatory life cycle management aligned with Intel's global standards and country-specific requirements.
WCS is committed to advancing wireless communication capabilities, supporting Intel’s leadership in the wireless ecosystem, and enabling next-generation connected experiences.
As a Silicon Packaging Architect/Engineer, you'll drive cutting-edge semiconductor packaging technology and architecture for WiFi, Bluetooth, and mmWave products, focusing on RF/Electrical, Thermal, Mechanical, Reliability, and Cost optimization.
What You'll Do
Strategic Leadership & Architecture:
Translate product requirements into comprehensive package architecture specifications
Lead technology trade-off decisions ensuring packages meet electrical, mechanical, thermal, and reliability standards
Lead Package level simulations (Mechanical and Thermal) to address specific risk areas
Define overall product package performance specifications and drive technology certification
Oversee end-to-end package development processes, from design through production
Technical Excellence & Innovation:
Troubleshoot complex packaging problems and develop innovative, cost-effective solutions
Research packaging assembly materials and properties, establishing specifications for suppliers
Perform mechanical and reliability simulations to optimize package design
Conduct thermal performance simulations using predictive FEA analysis
Cross-Functional Collaboration:
Partner with silicon, hardware, and package design teams to ensure high-quality deliverables
Coordinate with internal/external manufacturing partners (OSATs) and substrate suppliers
Support product co-design and layout teams as manufacturing liaison
Collaborate with Quality & Reliability teams to ensure products meet specifications
Complete DFMEA assessments with assembly suppliers to evaluate technology risks
Manufacturing & Process Management:
Ensure seamless transition from design to high-volume production
Design and validate Test Vehicles for process characterization
Provide consultation on packaging improvements and process optimization
Qualifications:
What We're Looking For
Education & Experience
Minimum Requirements:
Bachelor's degree in Mechanical Engineering, Electrical Engineering, Materials Science/Engineering, Physics, or related field 4 years industry experience
OR Master's degree in relevant field 3 years experience
OR PhD in relevant field 1 years experience
Required Technical Skills
2 years package assembly technology development experience
2 years packaging physics (mechanical and thermal) and/or materials experience
2 years package assembly manufacturing processes and HVM ramp experience
Preferred Qualifications
Semiconductor device physics and process engineering experience
RF Component Packaging experience (highly valued for wireless products)
Testing systems experience with hardware/software (Matlab, LabView)
Essential Skills
Strong project management capabilities
Proficiency in Microsoft Office Suite
Excellent communication and presentation abilities
Self-driven with strong problem-solving tenacity
Action-oriented mindset
Why This Role Matters
You'll be at the foref ... (truncated, view full listing at source)
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