ASIC Link Modeling Technical Leader

The application window is expected to close on: 05/30/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . Meet the Team Cisco’s Client Optics Group (COG) designs & delivers the high-speed optical transceivers, and platforms that power Cisco's core data center networking solutions. We specialize in the design and integration of innovative IM/DD optics and silicon photonic platforms that enable customers to deploy industry-leading optical technologies within data centers with unprecedented speed, capacity, and reliability. Come join us and take part in shaping COG’s ground-breaking optical solutions by designing, developing, and testing some of the most advanced pluggable, and Co-packaged Optics (CPO) being developed in the industry. You will work with Cisco's best-in-class Silicon Photonics team. Our team is responsible for driving the development and optimization of optical transceivers & modules (800G,1.6T & beyond) that seamlessly integrate with Cisco's routing, switching, and datacenter platforms, enabling customers to build scalable, high-performance networks that support emerging technologies including AI/ML workloads, and next-generation data center architectures. We are seeking a hardworking and experienced ASIC Link Modeling Engineer to join our team and be a collaborative modeler for Cisco's silicon photonics systems for next generation products for 100/200/400G per Lambda solutions. You will be a part of a wider team architecting and modeling high-speed SerDes, optical DSP (ODSP), die-to-die (D2D) interfaces, receive and transmit paths in silicon photonics modules and CPO/NPO solutions. Your Impact Develop system-level behavioral models and comprehensive link simulations for Cisco's silicon photonics systems, enabling performance analysis across high-speed SerDes, optical DSP, and die-to-die interfaces for next-generation 100G/200G/400G per Lambda solutions. Lead link budget analysis, channel modeling, and statistical simulations to evaluate jitter, noise, crosstalk, and bit error rate (BER) across transmit and receive paths. Define and optimize transceiver architectures including TX/RX equalization (FFE, CTLE, DFE), clock and data recovery behavior, and DSP algorithms through behavioral modeling and simulation. Debug complex link simulations, identify architectural bottlenecks, and correlate pre-silicon models with post-silicon lab measurements to validate design performance. Collaborate across cross-functional teams to develop IBIS-AMI models, create modeling documentation, and support product release from concept through production. Minimum Qualifications Bachelors 12 years of related experience, or Masters 8 years of related experience, or PhD 5 years of ASIC link modeling experience Proficiency in Python, C/C, and MATLAB for behavioral model development and automated analysis Proven understanding of high-speed communication theory, transmission line theory, SerDes, Ethernet, D2D PHY protocols, and DSP fundamentals Demonstrated experience with EDA and SI simulation tools (e.g., Keysight ADS, Synopsys HSPICE, Cadence) and link modeling methodologies Analytical, problem-solving, and debugging skills with excellent communication and teamwork abilities Preferred Qualifications Preferred experience 8-12 years. Experience with optical DSP (ODSP), integrated transceiver features, and PAM4 modulation techniques Familiarity with IBIS-AMI model development to support customer & system-level signal integrity simulations Experience with Linux-based development environments and scripting automation (Perl, TCL) Knowledge of ASIC/SoC design flow, understanding of multi-functional impacts on link performance (packaging, PCB, optics) Post-silicon validation experience and correlation of lab measurements with pre-silicon models Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in th ... (truncated, view full listing at source)