ASIC Physical Design Engineer

The application window is expected to close on: 05/29/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . Meet the Team Acacia, part of Cisco, provides innovative silicon-based high-speed optical interconnect products to accelerate network scalability through advancements in performance, capacity, and cost. Our DSP ASICs, silicon photonic PICs, and coherent modules empower cloud and service providers to meet the fast-growing demand for data. We have assembled a team of cross-functional experts capable of solving the challenges of next-generation optical interconnects, resulting in industry-leading, award-winning products. Come join us at Cisco, named the #1 world’s best workplaces, and do purposeful work that makes a global impact and gives back to a company culture that empowers an inclusive future for all. Your Impact As a Physical Design Engineer with Acacia, you will focus on the technical execution of high-performance ASIC designs. Working as an individual contributor, you will lead the RTL-to-GDSII implementation flow for advanced semiconductor nodes, ensuring that Acacia’s networking platforms meet rigorous power, performance, and area (PPA) targets. You will be responsible for the successful delivery of assigned blocks from specification through to tapeout. Implement end-to-end RTL-to-GDSII implementation for advanced nodes (sub-7nm to 2nm) Perform hierarchical floor planning, place and route, and clock/power distribution Conduct static timing analysis (STA) and drive timing closure for multi-mode/multi-corner designs Lead the physical design of assigned blocks, ensuring quality and alignment to project timelines Develop and maintain automated scripts to improve design flow efficiency and methodology Collaborate with RTL and DFT teams to debug and resolve complex physical implementation issues Implement test plans and participate in design reviews to ensure robust, high-quality work Implement ECO strategies and support sign-off processes Contribute to the refinement of design methodologies and best practices within the engineering team Document functional specifications and track progress for assigned project landmarks Minimum Qualifications Bachelors degree in Engineering 5 years of related experience, or Masters degree in Engineering 3 years of related experience. Demonstrated experience in ASIC physical design and implementation. Experience working with hierarchical floor planning, clock and power distribution, global signal and I/O planning along with physical convergence, timing closure, and hierarchical design methodology. Prior experience with power integrity analysis and working on designs >100M gates in advanced nodes. Preferred Qualifications Experience with Scripting using languages such as TCL, Perl, Python, etc. Place & Route experience using tools such as Cadence Innovus or Synopsys ICC2. Experience with formal equivalence check, timing closure, signal integrity, EMIR, physical verification DRC/LVS Synthesis experience including Synopsys DC/FC. Formal Verification experience using tools such Synopsys Formality or Cadence LEC Experience with Static Timing Analysis including tools such as Tempus. Experience with block level EMIR closure. Physical Verification experience including tools such as Synopsys ICV or Mentor Calibre. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the o ... (truncated, view full listing at source)