Physical Design Engineer for Core IP

Job Details: Job Description: As a member of Intel's CPU development team, you will have a front seat in designing the latest core IP to power cutting edge compute processors across client, server, IOTG and AI. We innovate state of the art microprocessor architecture on the most advanced and latest process technologies with a focus on power efficiency. Our core designs are present in nearly all segments of intels compute roadmap. Job responsibilities include but are not limited to: Perform physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing. Conduct all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conduct verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams. Possesse CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT. Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, low power synthesizable CPU. Optimize CPU design to improve product level parameters such as power, frequency, and area. Participate in the development and improvement of physical design methodologies and flow automation. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Minimum Qualifications: Bachelors in Computer Engineering or Electrical Engineering with 3 years of relevant work experience or M.S. in Computer Engineering or Electrical Engineering (or higher degree) with 2 years of relevant work experience. 2 years of experience in: Experience with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure PV convergence (including static timing and power analysis) Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electro-migration checks. Scripting in an interpreted language, minimum TCL in addition to at least one other (e.g. Perl, Python, Ruby) Experience in one or more of the following areas: Synthesis of a digital logic block, which was integrated into a large SoC or IP Preferred Qualifications: Experience in the following: Physical design best known practices concerning floor-planning, routing techniques, clock distribution Static Timing Analysis, Noise analysis, and reliability verification techniques RTL to GDS methodologies and formal equivalence Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations: Business group: Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic info ... (truncated, view full listing at source)