Senior Yield Engineer – Substrate & Advanced Packaging

Intel
US, Arizona, Phoenix$134k – $255kPosted 2 May 2026

Job Description

Job Details: Job Description: ​ Join Intel's Innovation Journey Are you passionate about driving breakthrough technologies that power the world's most advanced computing solutions? Intel Foundry Group is seeking a talented Senior Yield Engineer – Substrate & Advanced Packaging to join our Advanced Packaging Technology and Manufacturing team. In this role, you'll be at the forefront of semiconductor innovation, working with cutting-edge technology nodes and making direct impact on next-generation products that shape the future of computing. What You'll Do Drive Technology Excellence Through Data-Driven Insights Lead process development initiatives throughout complete technology node lifecycles by identifying and resolving critical yield limiters Perform advanced statistical analysis and create compelling data visualizations to build accurate process development roadmaps that achieve key technology yield milestones Develop innovative methods, processes, and systems to consolidate and analyze diverse big data sources, establishing optimal methodologies for defect mode understanding and yield modeling Transform Complex Data into Actionable Solutions Organize, interpret, and structure insights from fabrication process, defect, and electrical data while detecting anomalies and driving process improvements for yield enhancement Extract meaningful insights from both structured and unstructured data by synthesizing large data volumes using statistics, machine learning, and advanced coding techniques Develop sophisticated systems that transform complex experimental and manufacturing data into concrete yield improvement actions Collaborate Across Teams for Maximum Impact Execute new product introductions and enable design technology co-optimization through participation in factory task force design of experiments Create cross-functional partnerships across organizations to debug yield limiters in design, test, and process development areas Ensure manufacturability through comprehensive analysis of process and specification corners, working closely with design teams to resolve yield issues before manufacturing ramp Innovate with Advanced Tools and Methodologies Develop cutting-edge tools, multivariate algorithms, and methodologies for high-volume data analysis to identify root cause yield limiters Perform fault isolation and failure analysis using various advanced techniques including ATE testing, DFx software tools, optical probing, logic/circuit simulation, and emulation Develop measurement recipes that provide rapid, accurate feedback on product integrity to resolve yield and quality issues Behavioral traits that we are looking for: Strong analytical and problem‑solving skills Communicates clearly and effectively with cross‑functional teams, customers, and external partners Works effectively in ambiguous problem spaces and balances technical tradeoffs using sound engineering judgment Demonstrates ownership and accountability for technical outcomes and deliverables Collaborates productively across organizational boundaries and multi‑site teams Maintains a strong focus on design quality, documentation, and technical rigor Intel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life. See  Intel Benefits  for more details. Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Note: For information on Intel’s immigration sponsorship guidelines, please see Intel U.S. Immigration Sponsorship Information Minimum Qualifications and Experience : Candidate must possess a Masters degree in Materials Science and Engineering, Mechanical Engineering, Chemical Engineering, Electrical Engineering, Chemistry/Physics or related field and 5 years of ex ... (truncated, view full listing at source)
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