Principal Analog Circuit Design Engineer - SerDes

Job Details: Job Description: Designs, develops, and builds analog circuits in advanced process nodes for analog and mixedsignal IPs. Designs floorplans, performs circuit design, extracts chip parameters, and simulates analog behavior models. Creates test plans to verify design according to circuit and block microarchitecture specifications and evaluates test results. Verifies functionality to optimize circuit for power, performance, area, timing, and yield goals. Collaborates cross functionally to report design progress and collects, tracks, and resolves any performance and circuit design issues. Optimizes performance, power, area, and reduces leakage of circuits. Works with architecture and layout team to design circuit for best functionality, robustness, and electrical capabilities. As a principal engineer, recognized as a domain expert who influences and drives technical direction across Intel and industry. Develops and mentors other technical leaders, grows the community, acts as a change agent, and role models Intel values. Aligns organizational goals with technical vision, formulates technical strategy to deliver leadership solutions, and demonstrates a track record of relentless execution in bringing products and technologies to market. Qualifications: Minimum Qualifications• Master's degree in Electrical Engineering, Electronics Engineering, or related field.• 8+ years of experience in analog/mixed-signal circuit design for high-speed SerDes applications.• Proven expertise in one or more of the following areas: PLL, CDR, CTLE, DFE, ADC, or Transmitter (TX) design.• Strong understanding of high-speed communication standards such as PCIe (Gen5/Gen6) and Ethernet (100G/400G/800G).• Solid foundational knowledge of analog design principles-noise, jitter, matching, stability, and linearity.• Hands-on experience with advanced FinFET CMOS process technologies (7nm or below).• Proficiency in analog design and simulation tools such as Cadence Virtuoso/ADE, HSPICE, or equivalent.• Experience in silicon bring-up, post-silicon validation, and lab debug of analog circuits.• Excellent communication, documentation, and presentation skills.• Strong problem-solving attitude and ability to deliver under tight schedules in a collaborative environment.________________________________________Preferred Qualifications• Ph.D. in Electrical Engineering, Electronics Engineering, or related field.• 10+ years of experience in analog design for high-speed SerDes (56G/112G/224G) applications.• Deep expertise in transmitter and receiver architecture, CDR loops, equalization techniques, and advanced ADC architectures.• Familiarity with next-generation standards such as PCIe 6.0+, 800G/1.6T Ethernet, JESD, and other SerDes protocols.• Hands-on experience in behavioral modeling (Verilog-A), MATLAB-based analysis, and automation scripting (Python/Tcl/Perl).• Strong understanding of signal integrity, channel modeling, and system-level link performance.• Proven ability to mentor junior engineers, guide layout implementation, and drive design reviews.• Demonstrated leadership in cross-functional technical discussions and decision-making.• Team player with a collaborative mindset, willingness to share knowledge, and a hands-on approach to problem-solving. Job Type: Experienced Hire Shift: Shift 1 (Canada) Primary Location: Canada, Toronto Additional Locations: Business group: The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses. Posting Statement: All qualified applicants will receive consideration for employmen ... (truncated, view full listing at source)