Physical Design Engineer

Job Details: Job Description: We are seeking an Entry Level Physical Design Engineer for a timebound assignment to support blocklevel and chiplevel Physical Design execution on advanced technology nodes. The engineer will work as an individual contributor, under the guidance of senior Physical Design leads, and will be responsible for implementation, timing analysis, and physical design signoff tasks in support of project execution milestones. Qualifications: Key Responsibilities Execute blocklevel and chiplevel Physical Design implementation activities Perform floorplanning, placement, clock tree synthesis (CTS), and routing for assigned blocks Support Static Timing Analysis (STA) including setup, hold, and clock checks Run and analyze Physical Design signoff checks, including: DRC, LVS EM/IR checks Power integrity and reliability checks Debug timing and physical violations and support closure with guidance from PD/STA leads Support ECO implementation and final signoff closure Follow established methodologies, flows, and project guidelines Deliver assigned tasks with focus on quality, schedule, and execution discipline Minimum Qualifications Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field 0-2 years of industry experience or strong academic exposure in VLSI Physical Design / Backend Design Solid understanding of Physical Design fundamentals: Floorplanning, placement, CTS, routing Timing basics (setup/hold, clocking concepts) Familiarity with Physical Design and timing analysis flows Ability to work as an individual contributor under technical guidance Strong analytical, problemsolving, and learning mindset Preferred Qualifications Handson exposure to industry EDA tools (e.g., ICC2, Innovus, PrimeTime or equivalent) Academic projects or internships involving STA, EM/IR, or Physical Design signoff Scripting experience (Tcl / Python / Perl) Exposure to advanced technology nodes and lowpower design concepts Good written and verbal communication skills Job Type: Intel Contract Employee Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.