ASIC Engineer

<p><b>Job Title: ASIC Engineer<br />Location: San Jose, CA<br />Duration: 6 Months</b><br /><br /><b><u>Minimum Required Skills:</u></b><br />ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation,Synthesis /Conformal (Cadence Tool for formal verification)<br /><br /><b><u>Description:</u></b></p><p>Should have 2-5 years of experience in FPGA/ASIC Development<br />Build RTL designs of digital circuits using VHDL and System Verilog<br />Perform frontend design development and integration of large ASIC designs<br />Collaborate with Chip Architecture, Design Verification, and Physical Design teams to achieve first tapeout success.<br />Write design documents including high level interface descriptions and design descriptions.<br />Write function test cases and test benches to verify functionality of designs<br />Team work and proactive sharing of knowledge <br />Comfortable working in a fast paced environment.<br /></p> <p><span><b>ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation,Synthesis /Conformal (Cadence Tool for formal verification)</b></span><br /></p> <p>All your information will be kept confidential according to EEO guidelines.</p>