Memory Architect
TenstorrentNorth America$100k – $500kPosted 24 February 2026
Tech Stack
Job Description
<div class="content-intro"><p>Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.</p></div><p>Tenstorrent is at the forefront of AI technology, building next-generation computers where memory is a key component. We're seeking an innovative Memory Architect to push the boundaries of our memory chiplet architecture for AI and CPU applications. You'll work closely with fellow architects, cross-functional teams, and external partners to explore advanced memory technologies.</p>
<p>This role is<strong> </strong>remote or hybrid, based out of North America or South Korea.</p>
<p>We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.</p>
<p> </p>
<p><strong>Who You Are</strong></p>
<ul>
<li>You have a deep understanding of JEDEC standard DRAMs (GDDR, HBM, LPDDR, DDR) and their specifications.Experience with 3D-stacking, advanced packaging, custom memory, DFI, die-to-die interfaces, storage, and I/O protocols is a huge plus.</li>
<li>You bring 10+ years of experience in memory system architecture, scheduling algorithms, and controller architecture exploration and design. You have hands-on experience building performance/power simulators or developing memory IPs in HDL. A deep understanding of memory reliability and security is a strong plus.</li>
<li>You are a collaborative team player with excellent communication skills and a history of mentoring junior engineers.</li>
<li>A PhD with a focus on computer architecture or a strong research background (or a publication track record) is a strong plus.</li>
</ul>
<p> </p>
<p><strong>What We Need</strong></p>
<ul>
<li>Define the architecture and micro-architecture specifications for memory and I/O chiplets, focusing on state-of-the-art memory technology for AI and CPU applications.</li>
<li>Explore and evaluate next-generation memory technologies, analyzing trade-offs across key metrics like bandwidth, latency, and power to develop a strategic roadmap.</li>
<li>Develop and own a detailed performance and power modeling infrastructure to enable data-driven decisions for high-throughput, low-latency memory architectures.</li>
<li>Work closely with SoC design/verification, physical design, packaging, and systems engineering teams to ensure seamless integration. You will also communicate frequently with external partners and customers.</li>
</ul>
<p> </p>
<p><strong>What You Will Learn</strong></p>
<ul>
<li>How to lead architectural decisions and drive alignment across IP, SoC, and system software teams in a fast-paced and rapidly growing environment.</li>
<li>How complex chiplets are brought to life, from architecture specifications all the way to silicon fabrication, packaging, and mass production.</li>
<li>How Tenstorrent is designing next-generation chiplet-based SoCs that unify AI, CPU, Memory, I/O, and scale-out elements.</li>
<li>How to optimize data movement across the entire software-hardware stack.</li>
<li>You will exchange your expertise in the memory subsystem with fellow expert architects in AI, CPU, fabric, security, power, reliability, debug, system design, and scale-out.</li>
</ul>
<p> </p>
<p><em>Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, sk ... (truncated, view full listing at source)
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