Senior DFT Engineer, Architecture

<div class="content-intro"><p>Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.</p></div><p class="p1"><strong>Job title</strong></p> <p class="p2">Senior DFT Engineer</p> <p class="p1"><strong>Job description</strong></p> <p class="p3">We are looking for a person ready to take up the challenge of working in a high-profile project where we design and integrate multiple chiplets into a System-in-package, in collaboration with external stakeholders. You will work with Tenstorrent worldwide experts and leaders in the USA, Japan and other countries, and help us make our IP even better.</p> <p class="p2">In this role, you will be responsible for DFT implementation using industry standard tools for high-speed CPU core design.<span class="Apple-converted-space"> </span></p> <p class="p1"><strong>Your responsibilities</strong></p> <p class="p3">Integrate and verify test features in digital designs for effective manufacturing testing and silicon debug. Key responsibilities include:</p> <ul class="ul1"> <li class="li3"><span class="s1">Building entire chip-level DFT strategies</span></li> <li class="li3"><span class="s1">Inserting DFTs, including scan chains, memory BIST, and JTAG</span></li> <li class="li3"><span class="s1">Collaborating with RTL, physical design, and verification teams for testability throughout the design flow</span></li> <li class="li3"><span class="s1">Scripting and automating DFT flows using industry-standard EDA tools (e.g., Cadence, Synopsys, Siemens)</span></li> <li class="li3"><span class="s1">Running and analyzing ATPG and fault coverage reports</span></li> <li class="li3"><span class="s1">Supporting silicon bring-up and debug related to test features</span></li> <li class="li3"><span class="s1">Knowledge of advanced silicon technologies and methodologies for test coverage optimization</span></li> <li class="li3"><span class="s1">Experience with formal verification and signoff of inserted DFT logic</span></li> <li class="li3"><span class="s1">Strong communication and collaboration skills for cross-functional teamwork</span></li> </ul> <p class="p5"> </p> <p class="p1">Experience and qualifications</p> <ul class="ul1"> <li class="li3">Bachelor, Master or PhD degree in electrical, computer engineering or computer science.</li> <li class="li3">At least 10 years of relevant industry experience.</li> <li class="li3">Experience with DFT standard tools (e.g. Synopsys/Siemens), scripting languages (e.g., TCL, Python) is required.</li> <li class="li3">Experience with DFT planning, debug silicon by making SOC</li> <li class="li3">Willingness to work with others in a highly complex decision space.</li> <li class="li3">Skills at developing an DFT plan, monitoring key indicators and communicating resource needs, as well as scoping risk to deliver value on schedule.</li> <li class="li2">Excellent verbal and written communication in English, and collaboration skills.</li> </ul> <p class="p1">Nice to have</p> <ul class="ul1"> <li class="li3">Fluency in Japanese.</li> <li class="li2">Japanese work visa.</li> </ul><div class="content-conclusion"><p><em>This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technolog ... (truncated, view full listing at source)