Sr. Staff Product Development Engineer - Test Methodology Engineer

<div class="content-intro"><p>Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.</p></div><p><span style="font-size: 10pt;">Tenstorrent is seeking a Sr. Staff Test Methodology Engineer to help build the next generation of AI silicon and platforms, they will we need a to own the tools, systems, and processes that make our product and test engineers successful. The role will work across DFT, systems, software, and architecture to define how we bring up, validate, and scale high-volume production test for advanced AI devices. </span></p> <p><span style="font-size: 10pt;">This role is hybrid, based out of <strong>Santa Clara, CA</strong> or <strong>Austin, TX.</strong></span></p> <p><span style="font-size: 10pt;">We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.</span></p> <p style="line-height: 1.5;"> </p> <p><span style="font-size: 10pt;"><strong>Who You Are</strong></span></p> <ul> <li style="font-size: 10pt;"><span style="font-size: 10pt;">A senior semiconductor test engineering leader with 15 years experience, who has built and scaled ATE-based production test for complex SoCs.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Hands-on with Teradyne (UltraFlex/J750) and/or Advantest V93K and comfortable defining tester and handler strategies, not just using existing ones.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Fluent with revision control and CI/CD (gitlab, github, Bitbucket, pipelines) and passionate about robust, automated infrastructure.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Comfortable collaborating across DFT, systems, software, and architecture, and with OSAT partners, to drive low test-escape rates and high yield.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">A systems thinker who understands probe card/load board design considerations, fuse/eFuse programming, and production data analysis.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">A scripting-oriented engineer (Python, Perl, or TCL) who drives automation and efficiency across test flows and infrastructure.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Curious about next-generation advanced packaging (2.5D, chiplets) and how it changes test methodology.</span><br><br></li> </ul> <p><span style="font-size: 10pt;"><em> </em><strong>What We Need</strong></span></p> <ul> <li style="font-size: 10pt;"><span style="font-size: 10pt;">BS/MS in EE/ECE/CE with 15 years in semiconductor test engineering with hands-on experience with Teradyne UltraFlex/J750 and/or Advantest V93K.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Ability to define and specify tester and handler roadmaps aligned to product and technology needs.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Understanding of probe card and load board design and standardization.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Ownership of test program revision control and release automation pipelines and experience with distributed revision control (gitlab, github, Bitbucket) and CI/CD for test content.</span></li> <li style="font-size: 10pt;" ... (truncated, view full listing at source)