Senior Staff Analog Circuit Design Engineer - SerDes

Job Details: Job Description: Shape the Future of High-Speed Connectivity Are you passionate about pushing the boundaries of analog design? Join our elite SerDes team and help architect the next generation of high-speed interconnect solutions that power tomorrow's data centers, AI infrastructure, and communication networks. As a Senior Staff Analog Design Engineer, you'll be at the forefront of developing cutting-edge analog and mixed-signal circuits for blazing-fast 112G and 224G SerDes applications. This isn't just another engineering role – it's your opportunity to innovate, lead, and make a lasting impact on the semiconductor industry. Why This Role? Innovation at Scale: Work on industry-defining technologies that enable global connectivity Technical Excellence: Join a highly experienced team focused on breakthrough solutions Career Growth: Opportunity to mentor others while expanding your own expertise Collaborative Culture: Engage with brilliant minds across multiple disciplines Impact: Your designs will power the infrastructure of tomorrow's digital world Ready to engineer the future of high-speed communication? Join us in creating the analog circuits that will define the next decade of connectivity. This is more than a job; it's your chance to leave a lasting mark on the semiconductor industry. We're looking for self-driven innovators who thrive in collaborative environments and are passionate about pushing the limits of what's possible in analog design. What You'll Do Design & Innovate: Design high-performance analog blocks and subsystems that define industry standards Collaborate & Lead: Work alongside world-class system architects, digital designers, and layout engineers Validate & Optimize: Drive post-silicon validation and performance optimization initiatives Mentor & Guide: Shape the next generation of analog designers while providing technical leadership Problem-Solve: Tackle complex challenges in high-speed communication systems with creative solutions Communication skills: Strong documentation abilities and collaborative mindset Qualifications: Minimum Qualifications Master's degree in electrical/Electronic Engineering or related field 5+ years of proven experience in analog/mixed-signal circuit design for high-speed SerDes Experience in one or more domains: PLL, CDR, CTLE, DFE, ADC, or Transmitter design Standards knowledge: PCIe (Gen4/Gen5) and Ethernet (100G/400G) experience Technical mastery: Core analog design principles (noise, linearity, matching, stability) Process expertise: Hands-on experience with advanced FinFET CMOS technologies Tool proficiency: Cadence Virtuoso/ADE, HSPICE, or equivalent simulation platforms Lab experience: Silicon validation, measurements, and analog circuit debugging Preferred Qualifications Ph.D. in Electrical/Electronic Engineering 7+ years of specialized SerDes analog design experience Advanced knowledge: Transmitter/receiver design, CDR loops, equalization techniques Next-gen standards: PCIe 6.0, 800G Ethernet, JESD exposure Modeling expertise: Verilog-A, MATLAB simulations, automation scripting (Python, Tcl) System understanding: Signal integrity, channel modeling, link analysis Leadership qualities: Cross-functional collaboration and technical review contributions Job Type: Experienced Hire Shift: Shift 1 (Canada) Primary Location: Canada, Toronto Additional Locations: Business group: Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. Leading on policy, diversity, inclusion, education and sustainability, we create value ... (truncated, view full listing at source)